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Contents
1 Introduction...........................................................................................................15
1.1 1.2 1.3 1.4 Terminology ...................................................................................................16 Related Documents .......................................................................................17 Intel(R) 865G Chipset System Overview ..........................................................18 Intel(R) 82865G GMCH Overview ....................................................................20 1.4.1 Host Interface....................................................................................20 1.4.2 System Memory Interface .................................................................20 1.4.3 Hub Interface ....................................................................................21 1.4.4 Communications Streaming Architecture (CSA) Interface ................21 1.4.5 Multiplexed AGP and Intel(R) DVO Interface.......................................21 1.4.6 Graphics Overview............................................................................22 1.4.7 Display Interface ...............................................................................24 Clock Ratios...................................................................................................24 Host Interface Signals....................................................................................27 Memory Interface ...........................................................................................30 2.2.1 DDR SDRAM Channel A ..................................................................30 2.2.2 DDR SDRAM Channel B ..................................................................31 Hub Interface .................................................................................................32 Communication Streaming Architecture (CSA) Interface...............................32 AGP Interface ................................................................................................33 2.5.1 AGP Addressing Signals...................................................................33 2.5.2 AGP Flow Control Signals ................................................................34 2.5.3 AGP Status Signals ..........................................................................34 2.5.4 AGP Strobes .....................................................................................35 2.5.5 PCI Signals-AGP Semantics............................................................36 2.5.5.1 PCI Pins during PCI Transactions on AGP Interface ........37 2.5.6 Multiplexed Intel(R) DVOs on AGP ......................................................37 2.5.7 Intel(R) DVO-to-AGP Pin Mapping.......................................................39 Analog Display Interface ................................................................................40 Clocks, Reset, and Miscellaneous Signals ....................................................41 RCOMP, VREF, VSWING Signals.................................................................42 Power and Ground Signals ............................................................................43 GMCH Sequencing Requirements.................................................................44 Signals Used As Straps .................................................................................45 2.11.1 Functional Straps ..............................................................................45 2.11.2 Strap Input Signals............................................................................45 Full and Warm Reset States ..........................................................................46 Register Terminology.....................................................................................47 Platform Configuration Structure....................................................................48 Routing Configuration Accesses....................................................................50 3.3.1 Standard PCI Bus Configuration Mechanism ...................................50 3.3.2 PCI Bus #0 Configuration Mechanism ..............................................50 3.3.3 Primary PCI and Downstream Configuration Mechanism.................50 3.3.4 AGP/PCI_B Bus Configuration Mechanism ......................................51
1.5
2
Signal Description ..............................................................................................25
2.1 2.2 2.3 2.4 2.5
2.6 2.7 2.8 2.9 2.10 2.11 2.12
3
Register Description..........................................................................................47
3.1 3.2 3.3
Intel(R) 82865G/82865GV GMCH Datasheet
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3.4 3.5
3.6
I/O Mapped Registers.................................................................................... 52 3.4.1 CONFIG_ADDRESS--Configuration Address Register ................... 53 3.4.2 CONFIG_DATA--Configuration Data Register ................................ 54 DRAM Controller/Host-Hub Interface Device Registers (Device 0) ............... 55 3.5.1 VID--Vendor Identification Register (Device 0)................................ 57 3.5.2 DID--Device Identification Register (Device 0) ................................ 57 3.5.3 PCICMD--PCI Command Register (Device 0)................................. 58 3.5.4 PCISTS--PCI Status Register (Device 0) ........................................ 59 3.5.5 RID--Revision Identification Register (Device 0) ............................. 60 3.5.6 SUBC--Sub-Class Code Register (Device 0) .................................. 60 3.5.7 BCC--Base Class Code Register (Device 0) ................................... 60 3.5.8 MLT--Master Latency Timer Register (Device 0)............................. 61 3.5.9 HDR--Header Type Register (Device 0) .......................................... 61 3.5.10 APBASE--Aperture Base Configuration Register (Device 0)........... 62 3.5.11 SVID--Subsystem Vendor Identification Register (Device 0)........... 63 3.5.12 SID--Subsystem Identification Register (Device 0).......................... 63 3.5.13 CAPPTR--Capabilities Pointer Register (Device 0) ......................... 63 3.5.14 AGPM--AGP Miscellaneous Configuration Register (Device 0) ......................................................................................... 64 3.5.15 GC--Graphics Control Register (Device 0) ...................................... 65 3.5.16 CSABCONT--CSA Basic Control Register (Device 0)..................... 67 3.5.17 FPLLCONT-- Front Side Bus PLL Clock Control Register (Device 0) ......................................................................................... 68 3.5.18 PAM[0:6]--Programmable Attribute Map Registers (Device 0) ......................................................................................... 69 3.5.19 FDHC--Fixed Memory(ISA) Hole Control Register (Device 0) ......................................................................................... 71 3.5.20 SMRAM--System Management RAM Control Register (Device 0) ......................................................................................... 72 3.5.21 ESMRAMC--Extended System Management RAM Control (Device 0) ......................................................................................... 73 3.5.22 ACAPID--AGP Capability Identifier Register (Device 0) .................. 74 3.5.23 AGPSTAT--AGP Status Register (Device 0) ................................... 74 3.5.24 AGPCMD--AGP Command Register (Device 0).............................. 76 3.5.25 AGPCTRL--AGP Control Register (Device 0) ................................. 77 3.5.26 APSIZE--Aperture Size Register (Device 0) .................................... 78 3.5.27 ATTBASE--Aperture Translation Table Register (Device 0)............ 78 3.5.28 AMTT--AGP MTT Control Register (Device 0) ................................ 79 3.5.29 LPTT--AGP Low Priority Transaction Timer Register (Device 0) ......................................................................................... 80 3.5.30 TOUD--Top of Used DRAM Register (Device 0) ............................. 81 3.5.31 GMCHCFG--GMCH Configuration Register (Device 0)................... 82 3.5.32 ERRSTS--Error Status Register (Device 0)..................................... 84 3.5.33 ERRCMD--Error Command Register (Device 0) ............................. 85 3.5.34 SKPD--Scratchpad Data Register (Device 0) .................................. 86 3.5.35 CAPREG--Capability Identification Register (Device 0) .................. 86 PCI-to-AGP Bridge Configuration Register (Device 1) .................................. 87 3.6.1 VID1--Vendor Identification Register (Device 1).............................. 88 3.6.2 DID1--Device Identification Register (Device 1) .............................. 88 3.6.3 PCICMD1--PCI Command Register (Device 1)............................... 89 3.6.4 PCISTS1--PCI Status Register (Device 1) ...................................... 90 3.6.5 RID1--Revision Identification Register (Device 1) ........................... 91
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Intel(R) 82865G/82865GV GMCH Datasheet
3.7
SUBC1--Sub-Class Code Register (Device 1) ................................91 BCC1--Base Class Code Register (Device 1) .................................91 MLT1--Master Latency Timer Register (Device 1)...........................92 HDR1--Header Type Register (Device 1) ........................................92 PBUSN1--Primary Bus Number Register (Device 1) .......................92 SBUSN1--Secondary Bus Number Register (Device 1) ..................93 SUBUSN1--Subordinate Bus Number Register (Device 1) .............93 SMLT1--Secondary Bus Master Latency Timer Register (Device 1)..........................................................................................93 3.6.14 IOBASE1--I/O Base Address Register (Device 1) ...........................94 3.6.15 IOLIMIT1--I/O Limit Address Register (Device 1) ............................94 3.6.16 SSTS1--Secondary Status Register (Device 1) ...............................95 3.6.17 MBASE1--Memory Base Address Register (Device 1)....................96 3.6.18 MLIMIT1--Memory Limit Address Register (Device 1).....................97 3.6.19 PMBASE1--Prefetchable Memory Base Address Register (Device 1)..........................................................................................98 3.6.20 PMLIMIT1--Prefetchable Memory Limit Address Register (Device 1)..........................................................................................98 3.6.21 BCTRL1--Bridge Control Register (Device 1) ..................................99 3.6.22 ERRCMD1--Error Command Register (Device 1) .........................100 Integrated Graphics Device Registers (Device 2)........................................101 3.7.1 VID2--Vendor Identification Register (Device 2) ............................102 3.7.2 DID2--Device Identification Register (Device 2) ............................102 3.7.3 PCICMD2--PCI Command Register (Device 2) .............................103 3.7.4 PCISTS2--PCI Status Register (Device 2) ....................................104 3.7.5 RID2--Revision Identification Register (Device 2) .........................104 3.7.6 CC--Class Code Register (Device 2) .............................................105 3.7.7 CLS--Cache Line Size Register (Device 2) ...................................105 3.7.8 MLT2--Master Latency Timer Register (Device 2).........................105 3.7.9 HDR2--Header Type Register (Device 2) ......................................106 3.7.10 GMADR--Graphics Memory Range Address Register (Device 2)........................................................................................106 3.7.11 MMADR--Memory-Mapped Range Address Register (Device 2)........................................................................................107 3.7.12 IOBAR--I/O Decode Register (Device 2) .......................................107 3.7.13 SVID2--Subsystem Vendor Identification Register (Device 2)........................................................................................108 3.7.14 SID2--Subsystem Identification Register (Device 2)......................108 3.7.15 ROMADR--Video BIOS ROM Base Address Registers (Device 2)........................................................................................108 3.7.16 CAPPOINT--Capabilities Pointer Register (Device 2) ...................109 3.7.17 INTRLINE--Interrupt Line Register (Device 2) ...............................109 3.7.18 INTRPIN--Interrupt Pin Register (Device 2)...................................109 3.7.19 MINGNT--Minimum Grant Register (Device 2) ..............................110 3.7.20 MAXLAT--Maximum Latency Register (Device 2) .........................110 3.7.21 PMCAPID--Power Management Capabilities Identification Register (Device 2) .........................................................................110 3.7.22 PMCAP--Power Management Capabilities Register (Device 2)........................................................................................111 3.7.23 PMCS--Power Management Control/Status Register (Device 2)........................................................................................111 3.7.24 SWSMI--Software SMI Interface Register (Device 2) ....................112
3.6.6 3.6.7 3.6.8 3.6.9 3.6.10 3.6.11 3.6.12 3.6.13
Intel(R) 82865G/82865GV GMCH Datasheet
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3.8
3.9
3.10
PCI-to-CSA Bridge Registers (Device 3) ..................................................... 113 3.8.1 VID3--Vendor Identification Register (Device 3)............................ 114 3.8.2 DID3--Device Identification Register (Device 3) ............................ 114 3.8.3 PCICMD3--PCI Command Register (Device 3)............................. 115 3.8.4 PCISTS3--PCI Status Register (Device 3) .................................... 116 3.8.5 RID3--Revision Identification Register (Device 3) ......................... 117 3.8.6 SUBC3--Class Code Register (Device 3) ...................................... 117 3.8.7 BCC3--Base Class Code Register (Device 3) ............................... 117 3.8.8 MLT3--Master Latency Timer Register (Device 3)......................... 118 3.8.9 HDR3--Header Type Register (Device 3) ...................................... 118 3.8.10 PBUSN3--Primary Bus Number Register (Device 3)..................... 118 3.8.11 SBUSN3--Secondary Bus Number Register (Device 3) ................ 119 3.8.12 SMLT3--Secondary Bus Master Latency Timer Register (Device 3) ....................................................................................... 119 3.8.13 IOBASE3--I/O Base Address Register (Device 3) ......................... 120 3.8.14 IOLIMIT3--I/O Limit Address Register (Device 3) .......................... 120 3.8.15 SSTS3--Secondary Status Register (Device 3)............................. 121 3.8.16 MBASE3--Memory Base Address Register (Device 3).................. 122 3.8.17 MLIMIT3--Memory Limit Address Register (Device 3)................... 123 3.8.18 PMBASE3--Prefetchable Memory Base Address Register (Device 3) ....................................................................................... 124 3.8.19 PMLIMIT3--Prefetchable Memory Limit Address Register (Device 3) ....................................................................................... 124 3.8.20 BCTRL3--Bridge Control Register (Device 3)................................ 125 3.8.21 ERRCMD3--Error Command Register (Device 3) ......................... 126 3.8.22 CSACNTRL--CSA Control Register (Device 3) ............................. 126 Overflow Configuration Registers (Device 6)............................................... 127 3.9.1 VID6--Vendor Identification Register (Device 6)............................ 127 3.9.2 DID6--Device Identification Register (Device 6) ............................ 128 3.9.3 PCICMD6--PCI Command Register (Device 6)............................. 128 3.9.4 PCISTS6--PCI Status Register (Device 6) .................................... 129 3.9.5 RID6--Revision Identification Register (Device 6) ......................... 129 3.9.6 SUBC6--Sub-Class Code Register (Device 6) .............................. 130 3.9.7 BCC6--Base Class Code Register (Device 6) ............................... 130 3.9.8 HDR6--Header Type Register (Device 6) ...................................... 130 3.9.9 BAR6--Memory Delays Base Address Register (Device 6)........... 131 3.9.10 SVID6--Subsystem Vendor Identification Register (Device 6) ....................................................................................... 131 3.9.11 SID6--Subsystem Identification Register (Device 6)...................... 131 Device 6 Memory-Mapped I/O Register Space ........................................... 132 3.10.1 DRB[0:7]--DRAM Row Boundary Register (Device 6, MMR) ............................................................................. 132 3.10.2 DRA--DRAM Row Attribute Register (Device 6, MMR) ................. 134 3.10.3 DRT--DRAM Timing Register (Device 6, MMR) ............................ 135 3.10.4 DRC--DRAM Controller Mode Register (Device 6, MMR) ............. 136 System Memory Address Ranges ............................................................... 139 Compatibility Area........................................................................................ 141 Extended Memory Area ............................................................................... 143 4.3.1 15 MB-16 MB Window ................................................................... 143 4.3.2 Pre-Allocated Memory .................................................................... 144
4
System Address Map ...................................................................................... 139
4.1 4.2 4.3
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Intel(R) 82865G/82865GV GMCH Datasheet
4.4
AGP Memory Address Ranges....................................................................146 Processor Front Side Bus (FSB)..................................................................147 5.1.1 FSB Dynamic Bus Inversion ...........................................................147 5.1.2 FSB Interrupt Overview...................................................................148 5.1.2.1 Upstream Interrupt Messages .........................................148 System Memory Controller ..........................................................................149 5.2.1 DRAM Technologies and Organization...........................................150 5.2.2 Memory Operating Modes ..............................................................150 5.2.2.1 Dynamic Addressing Mode..............................................151 5.2.3 Single-Channel (SC) Mode .............................................................151 5.2.3.1 Linear Mode.....................................................................151 5.2.3.2 Tiled Mode.......................................................................151 5.2.4 Memory Address Translation and Decoding ...................................151 5.2.5 Memory Organization and Configuration ........................................156 5.2.6 Configuration Mechanism for DIMMS .............................................157 5.2.6.1 Memory Detection and Initialization.................................157 5.2.6.2 SMBus Configuration and Access of the Serial Presence Detect Ports.....................................................................157 5.2.6.3 Memory Register Programming.......................................157 5.2.7 Memory Thermal Management.......................................................158 5.2.7.1 Determining When to Thermal Manage...........................158 Accelerated Graphics Port (AGP) ................................................................158 5.3.1 GMCH AGP Support.......................................................................159 5.3.2 Selecting between AGP 3.0 and AGP 2.0 ......................................159 5.3.3 AGP 3.0 Downshift (4X Data Rate) Mode.......................................159 5.3.3.1 Mechanism for Detecting AGP 2.0, AGP 3.0, or Intel(R) DVO.......................................................................160 5.3.4 AGP Target Operations ..................................................................162 5.3.5 AGP Transaction Ordering..............................................................162 5.3.6 Support for PCI-66 Devices ............................................................163 5.3.7 8X AGP Protocol.............................................................................163 5.3.7.1 Fast Writes ......................................................................163 5.3.7.2 PCI Semantic Transactions on AGP ...............................163 Integrated Graphics Controller.....................................................................164 5.4.1 3D Engine .......................................................................................165 5.4.1.1 Setup Engine ...................................................................165 5.4.1.2 Scan Converter................................................................166 5.4.1.3 2D Functionality...............................................................166 5.4.1.4 Texture Engine ................................................................166 5.4.1.5 Raster Engine..................................................................168 5.4.2 2D Engine .......................................................................................172 5.4.3 Video Engine...................................................................................173 5.4.4 Planes .............................................................................................173 5.4.4.1 Cursor Plane....................................................................173 5.4.4.2 Overlay Plane ..................................................................174 5.4.5 Pipes ...............................................................................................175 Display Interfaces ........................................................................................175 5.5.1 Analog Display Port Characteristics................................................176 5.5.2 Digital Display Interface ..................................................................177 5.5.2.1 Digital Display Channels - Intel(R) DVOB and Intel(R) DVOC ... 177
5
Functional Description ...................................................................................147
5.1
5.2
5.3
5.4
5.5
Intel(R) 82865G/82865GV GMCH Datasheet
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5.6 5.7 5.8
5.5.3 Synchronous Display ...................................................................... 180 Power Management..................................................................................... 180 5.6.1 Supported ACPI States................................................................... 180 Thermal Management.................................................................................. 181 5.7.1 External Thermal Sensor Interface Overview ................................. 181 5.7.1.1 External Thermal Sensor Usage Model .......................... 182 Clocking ....................................................................................................... 183 Absolute Maximum Ratings ......................................................................... 185 Thermal Characteristics............................................................................... 185 Power Characteristics.................................................................................. 186 Signal Groups .............................................................................................. 186 DC Parameters ............................................................................................ 189 DAC ............................................................................................................. 194 6.6.1 DAC DC Characteristics ................................................................. 194 6.6.2 DAC Reference and Output Specifications..................................... 194 6.6.3 DAC AC Characteristics.................................................................. 195 GMCH Ballout.............................................................................................. 197 GMCH Package Information........................................................................ 209 XOR Test Mode Initialization ....................................................................... 211 XOR Chain Definition................................................................................... 213 No AGP Interface......................................................................................... 222 Intel(R) 82865G / 82865GV Signal Differences .............................................. 222 9.2.1 Functional Straps ............................................................................ 222 Intel(R) 82865G / 82865GV Register Differences........................................... 223 9.3.1 DRAM Controller/Host-Hub Interface Device Registers (Device 0) ....................................................................................... 223 9.3.1.1 Device 0 Registers Not in 82865GV................................ 223 9.3.1.2 Device 0 Register Bit Differences.................................... 224 9.3.2 Host-to-AGP Bridge Registers (Device 1)....................................... 226 Synchronous Display Differences ................................................................ 226
6
Electrical Characteristics .............................................................................. 185
6.1 6.2 6.3 6.4 6.5 6.6
7
Ballout and Package Information............................................................... 197
7.1 7.2
8
Testability ............................................................................................................ 211
8.1 8.2
9
Intel(R) 82865GV GMCH..................................................................................... 221
9.1 9.2 9.3
9.4
10 11
Intel(R) 82865GV GMCH Ballout..................................................................... 227 Intel(R) 82865GV GMCH Testability .............................................................. 241
11.1 11.2 XOR Test Mode Initialization ....................................................................... 241 XOR Chain Definition................................................................................... 243
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Intel(R) 82865G/82865GV GMCH Datasheet
Figures
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Intel(R) 865G Chipset System Block Diagram..................................................19 Intel(R) 82865G GMCH Interface Block Diagram .............................................26 Intel(R) 865G Chipset System Clock and Reset Requirements .......................44 Full and Warm Reset Waveforms ..................................................................46 Conceptual Intel(R) 865G Chipset Platform PCI Configuration Diagram .........49 Configuration Mechanism Type 0 Configuration Address-to-PCI Address Mapping .................................................................51 Configuration Mechanism Type 1 Configuration Address-to-PCI Address Mapping .................................................................52 PAM Register Attributes.................................................................................70 Memory System Address Map.....................................................................140 Detailed Memory System Address Map......................................................140 Single-Channel Mode Operation..................................................................149 Dual-Channel Mode Operation ....................................................................149 GMCH Graphics Block Diagram ..................................................................164 Platform External Sensor .............................................................................182 Intel(R) 865G Chipset System Clocking Block Diagram .................................183 Intel(R) 82865G GMCH Ballout Diagram (Top View--Left Side) ...................198 Intel(R) 82865G GMCH Ballout Diagram (Top View--Right Side) .................199 Intel(R) 82865G GMCH Package Dimensions (Top and Side Views) ............209 Intel(R) 82865G GMCH Package Dimensions (Bottom View) ........................210 XOR Toggling of HCLKP and HCLKN .........................................................211 XOR Testing Chains Tested Sequentially....................................................212 Intel(R) 865GV Chipset System Block Diagram .............................................221 Intel(R) 82865GV GMCH Ballout Diagram (Top View--Left Side) .................228 Intel(R) 82865GV GMCH Ballout Diagram (Top View--Right Side)...............229 XOR Toggling of HCLKP and HCLKN .........................................................241 XOR Testing Chains Tested Sequentially....................................................242
Intel(R) 82865G/82865GV GMCH Datasheet
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Tables
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 General Terminology ..................................................................................... 16 System Memory Clock Ratios........................................................................ 24 Intel(R) DVO-to-AGP Pin Mapping ................................................................... 39 Internal GMCH Device Assignment ............................................................... 49 Configuration Address Decoding ................................................................... 51 DRAM Controller/Host-Hub Interface Device Register Address Map (Device 0) ................................................................................ 55 PAM Register Attributes ................................................................................ 70 PCI-to-AGP Bridge PCI Configuration Register Address Map (Device 1) ..... 87 VGAEN and MDAP Field Definitions ............................................................. 99 Integrated Graphics Device PCI Register Address Map (Device 2) ............ 101 PCI-to-CSA Bridge Configuration Register Address Map (Device 3) .......... 113 VGAEN and MDAP Definitions .................................................................... 125 Overflow Device Configuration Register Address Map (Device 6) .............. 127 Device 6 Memory-Mapped I/O Register Address Map ................................ 132 Memory Segments and Their Attributes ...................................................... 141 Pre-Allocated Memory ................................................................................. 144 System Memory Capacity............................................................................ 149 GMCH Memory Controller Operating Modes............................................... 150 DRAM Address Translation (Single-Channel Mode) (Non-Dynamic Mode)................................................................................... 152 DRAM Address Translation (Dual-Channel Mode, Discrete) (Non-Dynamic Mode)................................................................................... 152 DRAM Address Translation (Dual-Channel Mode, Internal Gfx) (Non-Dynamic Mode)................................................................................... 153 DRAM Address Translation (Single-Channel Mode) (Dynamic Mode) .......................................................................................... 154 DRAM Address Translation (Dual-Channel Mode, Discrete) (Dynamic Mode) .......................................................................................... 155 RAM Address Translation (Dual-Channel Mode, Internal Gfx) (Dynamic Mode) .......................................................................................... 156 Supported DDR DIMM Configurations......................................................... 156 Data Bytes on DIMM Used for Programming DRAM Registers................... 157 AGP Support Matrix..................................................................................... 159 AGP 3.0 Downshift Mode Parameters......................................................... 160 Pin and Strap Values Selecting Intel(R) DVO, AGP 2.0, and AGP 3.0 .......... 161 AGP 3.0 Commands Compared to AGP 2.0 ............................................... 162 Supported Data Rates ................................................................................. 162 Display Port Characteristics......................................................................... 176 Analog Port Characteristics ......................................................................... 176 Absolute Maximum Ratings ......................................................................... 185 Power Characteristics.................................................................................. 186 Signal Groups .............................................................................................. 187 DC Operating Characteristics ...................................................................... 189 DC Characteristics....................................................................................... 191 DAC DC Characteristics .............................................................................. 194 DAC Reference and Output Specifications.................................................. 194 DAC AC Characteristics .............................................................................. 195 Intel(R) 82865G Ball List by Signal Name ...................................................... 201 XOR Chain Outputs ..................................................................................... 213
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Intel(R) 82865G/82865GV GMCH Datasheet
44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67
XOR Chain 0 (60 Inputs) Output Pins: SDM_A0, SDM_B0 .........................214 XOR Chain 1 (33 Inputs) Output Pins: SDM_A1, SDM_B1 .........................215 XOR Chain 2 (44 Inputs) Output Pins: SDM_A2, SDM_B2 .........................215 XOR Chain 3 (41 Inputs) Output Pins: SDM_A3, SDM_B3 .........................216 XOR Chain 4 (40 Inputs) Output Pins: SDM_A4, SDM_B4 .........................216 XOR Chain 5 (44 Inputs) Output Pins: SDM_A5, SDM_B5 .........................217 XOR Chain 6 (40 Inputs) Output Pins: SDM_A6, SDM_B6 .........................217 XOR Chain 7 (45 Inputs) Output Pins: SDM_A7, SDM_B7 .........................218 XOR Chain 8 (40 Inputs) Output Pins: SDM_A8, SDM_B8 .........................218 XOR Chain 9 (62 Inputs) Output Pins: RS2#, DEFER#...............................219 XOR Excluded Pins .....................................................................................220 Intel(R) 82865GV Ball List by Signal Name ....................................................231 XOR Chain Outputs .....................................................................................243 XOR Chain 0 (60 Inputs) Output Pins: SDM_A0, SDM_B0 .........................244 XOR Chain 1 (33 Inputs) Output Pins: SDM_A1, SDM_B1 .........................245 XOR Chain 2 (44 Inputs) Output Pins: SDM_A2, SDM_B2 .........................245 XOR Chain 3 (41 Inputs) Output Pins: SDM_A3, SDM_B3 .........................246 XOR Chain 4 (40 Inputs) Output Pins: SDM_A4, SDM_B4 .........................246 XOR Chain 5 (44 Inputs) Output Pins: SDM_A5, SDM_B5 .........................247 XOR Chain 6 (40 Inputs) Output Pins: SDM_A6, SDM_B6 .........................247 XOR Chain 7 (45 Inputs) Output Pins: SDM_A7, SDM_B7 .........................248 XOR Chain 8 (40 Inputs) Output Pins: HTRDY#, BPRI# .............................248 XOR Chain 9 (62 Inputs) Output Pins: RS2#, DEFER#...............................249 XOR Excluded Pins .....................................................................................250
Intel(R) 82865G/82865GV GMCH Datasheet
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Revision History
Revision -001 -002 -003 -004 -005 * Initial Release * Corrected A0-A3 ACAPID Register Default Value in Table 6, Section 3.5. * Corrected bit A1 in Table 24, RAM Address Translation, 512mb, 64Mx8, from bit 15 to 16. * Added 82865GV information * Replaced Figure 19 in Section 7.2 Description Date May 2003 June 2003 June 2003 September 2003 February 2004
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Intel(R) 82865G/82865GV GMCH Datasheet
Intel(R) 82865G GMCH Features
I Host Interface Support
-- Intel(R) Pentium(R) 4 processors with 512-KB L2 cache on 0.13 micron process / Pentium 4 processor on 90 nm process -- VTT 1.1 V - 1.55 V ranges -- 64-bit FSB frequencies of 400 MHz (100 MHz bus clock), 533 MHz (133 MHz bus clock), and 800 MHz (200 MHz bus clock). Maximum theoretical BW of 6.4 GB/s. -- FSB Dynamic Bus Inversion on the data bus -- 32-bit addressing for access to 4 GB of memory space -- 12-deep In Order Queue -- AGTL+ On-die Termination (ODT) -- Hyper-Threading Technology -- Dual-channel (128 bits wide) DDR memory interface -- Single-channel (64 bits wide) DDR operation supported -- Symmetric and asymmetric memory dual-channel upgrade supported -- 128-Mb, 256-Mb, 512-Mb technologies implemented as x8, x16 devices -- Four bank devices -- Non-ECC, un-buffered DIMMS only -- Maximum of two DIMMs per channel, with each DIMM having one or two rows -- Up to 4 GB system memory -- Supports up to 16 simultaneously-open pages (four per row) in dual-channel mode and up to 32 open pages in single-channel mode -- 4-KB to 64-KB page sizes (4 KB to 32 KB in single-channel, 8 KB to 64 KB in dual-channel) -- Supports opportunistic refresh -- Suspend-to-RAM support using CKE -- SPD (Serial Presence Detect) Scheme for DIMM Detection supported -- Supports selective Command-Per-Clock (selective CPC) Accesses -- DDR (Double Data Rate type 1) Support - Supports maximum of two DDR DIMMs per channel, single-sided and/or double-sided - Supports DDR266, DDR333, DDR400 DIMM modules - Supports DDR channel operation at 266 MHz, 333 MHz and 400 MHz with a Peak BW of 2.1 GB/s, 2.7 GB/s, and 3.2GB/s respectively per channel - Burst length of 4 and 8 for single-channel (32 or 64 bytes per access, respectively); for dual-channel a burst of 4 (64 bytes per access) - Supports SSTL_2 signaling
I AGP Interface Support
-- A single AGP device -- AGP 3.0 with 4X / 8X AGP data transfers and 4X / 8X fast writes, respectively -- 32-bit 4X/8X data transfers and 4X/8X fast writes -- Peak BW of 2 GB/s. -- 0.8 V and 1.5 V AGP signalling levels; no 3.3 V support -- AGP 2.0 1X/4X AGP data transfers and 4X fast writes -- 32-deep AGP request queue -- Core Frequency of 266 MHz -- VGA/UMA Support -- High Performance 3D Setup and Render Engine -- High-Quality/Performance Texture Engine -- 3D Graphics Rendering Enhancements -- 2D Graphics -- Video DVD/PC-VCR -- Video Overlay -- Video Mixer Render Supported (VMR) -- Bi-Cubic Filter Support -- AGP signals multiplexed with two DVO ports (ADD card supported) -- Multiplexed Digital Display Channels (Supported with ADD Card) -- 350 MHz Integrated 24-bit RAMDAC -- Up to 2048x1536 @ 75 Hz refresh -- Hardware Color Cursor -- DDC2B Compliant Interface -- Simultaneous Display options with digital display -- Two channels multiplexed with AGP -- 165 MHz dot clock on each 12-bit interface -- Can combine two, 12-bit channels to form one, 24-bit interface Supports flat panels up to 2048x1536 @ 60 Hz or digital CRT/HDTV at 1920x1080 @ 85 Hz -- Supports Hot Plug and Display -- Supports LVDS, TMDS transmitters or TV-out encoders -- ADD card utilizes AGP connector -- Supports one additional flat panel (dCRT) and/or one TV (only when using internal GFX) -- Three Display Control interfaces (I2C/DDC) multiplexed on AGP -- 37.5 mm x 37.5 mm Flip Chip Ball Grid Array (FC-BGA) package -- 932 solder balls with variable ball pitch
I Integrated Graphics
I System Memory Controller Support
I Display Interfaces
I Analog Display Support
I Digital Display Channels
I GMCH Package
I Communication Streaming Architecture (CSA) Interface
-- Gigabit Ethernet (GbE) communication devices supported on the CSA interface (e.g., Intel(R) 82547EI GbE controller) -- Supports 8-bit Hub Interface 1.5 electrical/transfer protocol -- 266 MB/s point-to-point connection -- 1.5 V operation -- Supports Hub Interface 1.5 electrical/transfer protocol -- 266 MB/s point-to-point connection to the ICH5 -- 66 MHz base clock -- 1.5 V operation
I Hub Interface (HI)
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Intel(R) 82865G/82865GV GMCH Datasheet
Introduction
Introduction
1
The Intel(R) 82865G and the Intel(R)82865GV chipsets are designed for use in desktop systems based on an Intel(R) Pentium(R) 4 processor with 512-KB L2 cache on 0.13 micron process in the 478-pin package or the Intel(R) Pentium(R) 4 processor on 90 nm process, and supports FSB frequencies of 400 MHz, 533 MHz, and 800 MHz. The 82865G GMCH is part of the Intel(R) 865G chipset, the 82865GV GMCH is part of the Intel(R) 865GV chipset. Each chipset contains two main components: Graphics and Memory Controller Hub (GMCH) for the host bridge and I/O Controller Hub for the I/O subsystem. The GMCH provides the processor interface, system memory interface, hub interface, CSA interface and other additional interfaces in an 865G/ 865GV chipset desktop platform. Each GMCH contains an integrated graphics controller (IGD). The 865G /865GV chipset use either the 82801EB ICH5 or 82801ER ICH5R for the I/O Controller Hub. This document is the datasheet for the 82865G and the 82865GV Graphics and Memory Controller Hub (GMCH) component. The following are the key feature differences between the 82865G GMCH and 82865GV GMCH:
* AGP Interface
-- 82865G supports AGP. The AGP interface signals are multiplexed with the Intel(R) DVO interface signals. The 82865GV does not support AGP. The Intel(R) 865G/865GV chipset platform supports the following processors:
* Intel(R) Pentium(R) 4 processor with 512-KB L2 cache on 0.13 micron process in the 478-pin
package.
* Intel(R) Pentium(R) 4 processor on 90 nm process.
Note: Unless otherwise specified, the term processor in this document refers to the Pentium 4 processor with 512-KB L2 cache on 0.13 micron process in the 478-pin package and the Pentium 4 processor on 90 nm process. Unless otherwise specified, the term ICH5 in this document refers to both the 82801EB ICH5 and 82801ER ICH5R. Chapter 1 through Chapter 8 describe the 82865G GMCH. The 82865GV GMCH is described in Chapter 9 through Chapter 11.
Note:
Intel(R) 82865G/82865GV GMCH Datasheet
15
Introduction
1.1
Table 1.
Terminology
This section provides the definitions of some of the terms used in this document. General Terminology (Sheet 1 of 2)
Terminology Description Accelerated Graphics Port. In this document AGP refers to the AGP/PCI interface that is in the GMCH. The GMCH AGP interface supports only 0.8 V/1.5 V AGP 2.0/AGP 3.0 compliant devices using PCI (66 MHz), AGP 1X (66 MHz), 4X (266 MHz), and 8X (533 MHz) transfers. GMCH does not support any 3.3 V devices. For AGP 2.0, PIPE# and SBA addressing cycles and their associated data phases are generally referred to as AGP transactions. FRAME# cycles are generally referred to as AGP/PCI transactions. DRAM chips are divided into multiple banks internally. Commodity parts are all 4 bank, which is the only type the GMCH supports. Each bank acts somewhat like a separate DRAM, opening and closing pages independently, allowing different pages to be open in each. Most commands to a DRAM target a specific bank, but some commands (i.e., Precharge All) are targeted at all banks. Multiple banks allows higher performance by interleaving the banks and reducing page miss cycles. In the GMCH a DRAM channel is the set of signals that connect to one set of DRAM DIMMs. The GMCH has two DRAM channels, (a pair of DIMMs added at a time, one on each channel). The GMCH internal base logic. The column address selects one DRAM location, or the starting location of a burst, from within the open page on a read or write command. Terminology often used to describe a DIMM that contains two DRAM rows. Generally, a double-sided DIMM contains two rows, with the exception noted above. This terminology is not used in this document. Double Data Rate SDRAM. DDR describes the type of DRAMs that transfer two data items per clock on each pin. This is the only type of DRAM supported by the GMCH. A Full GMCH Reset is defined in this document when RSTIN# is asserted. Graphics Aperture Re-map Table. GART is a table in memory containing the page re-map information used during AGP aperture address translations. Graphics and Memory Controller Hub. The GMCH component contains the processor interface, SDRAM controller, AGP interface, CSA interface and an integrated 3D/2D/display graphics core. It communicates with the I/O controller hub (Intel(R) ICH5) over a proprietary interconnect called HI. Graphics Translation Look-aside Buffer. A cache used to store frequently used GART entries. The internal graphics related logic in the GMCH. Hub Interface. HI is the proprietary hub interface that connects the GMCH to the ICH5. In this document HI cycles originating from or destined for the primary PCI interface on the ICH5 are generally referred to as HI/PCI or simply HI cycles. This term is used synonymously with processor. Fifth generation IO Controller Hub component that contains additional functionality compared to the ICH4. Integrated Graphics Device. IGD refers to the graphics device integrated into the GMCH. The physical PCI bus that is driven directly by the ICH5 component. Communication between PCI and the GMCH occurs over the hub interface. Note that even though the Primary PCI bus is referred to as PCI, it is not PCI Bus 0 from a configuration standpoint. Processor Front-Side Bus. This is the processor system bus. A group of DRAM chips that fill out the data bus width of the system and are accessed in parallel by each DRAM command.
AGP
Bank
Channel Chipset Core Column Address Double-Sided DIMM DDR Full Reset GART
GMCH
GTLB Graphics Core HI Host Intel(R) ICH5 IGD Primary PCI FSB Row
16
Intel(R) 82865G/82865GV GMCH Datasheet
Introduction
Table 1.
General Terminology (Sheet 2 of 2)
Terminology Row Address Description The row address is presented to the DRAMs during an Activate command, and indicates which page to open within the specified bank (the bank number is presented also). Processor-to-GMCH interface. The compatible mode of the Scalable Bus is the P6 Bus. The enhanced mode of the Scalable Bus is the P6 Bus plus enhancements primarily consisting of source synchronous transfers for address and data, and FSB interrupt delivery. The Intel(R) Pentium(R) 4 processor implements a subset of the enhanced mode. Terminology often used to describe a DIMM that contains one DRAM row. Usually one row fits on a single side of the DIMM allowing the backside to be empty. Single Data Rate SDRAM. Synchronous Dynamic Random Access Memory. The physical PCI interface that is a subset of the AGP bus driven directly by the GMCH. It supports a subset of 32-bit, 66 MHz PCI 2.0 compliant components, but only at 1.5 V (not 3.3 V or 5 V). Stub Series Terminated Logic for 2.6 Volts (DDR)
Scalable Bus Single-Sided DIMM SDR SDRAM Secondary PCI SSTL_2
1.2
Related Documents
Document Document Number/ Location http://developer.intel.com/ design/chipsets/designex/ 252518.htm http://developer.intel.com/ design/chipsets/designex/ 252519.htm http://developer.intel.com/ design/chipsets/schematics/ 252813.htm http://developer.intel.com/ design/chipsets/schematics/ 300683.htm http://developer.intel.com/ design/chipsets/schematics/ 300684.htm http://developer.intel.com/ design/chipsets/specupdt/ 252517.htm http://developer.intel.com/ design/pentium4/datashts/ 298643.htm http://developer.intel.com/ design/pentium4/datashts/ 300561.htm http://developer.intel.com/ design/Pentium4/guides/ 300564.htm www.jedec.org
Intel(R) 865G/865GV/865PE/865P Chipset Platform Design Guide
Intel(R) 865G/865GV/865PE/865P Chipset Thermal Design Guide
Intel(R) 865G/865GV/865PE/865P Chipset Schematics Intel(R) 865G/865GV/865PE/865P Chipset CRB Schematics Addendum for the Intel(R) Pentium(R) 4 processor on 90 nm Process w/Loadline A Platforms 2 Phase VR Intel(R) 865G/865GV/865PE/865P Chipset CRB Schematics Addendum for the Intel(R) Pentium(R) 4 processor on 90 nm Process w/Loadline A Platforms 3 Phase VR Intel(R) 82801EB I/O Controller Hub 5 (ICH5) and Intel(R) 82801ER I/O Controller Hub 5R (ICH5R) Datasheet Intel(R) Pentium(R) 4 processor with 512-KB L2 Cache on 0.13 Micron Process Datasheet Intel(R) Pentium(R) 4 processor on 90 nm Process Datasheet Intel(R) Pentium(R) 4 processor on 90 nm Process Thermal and Mechanical Design Guide JEDEC Double Data Rate (DDR) SDRAM Specification
Intel(R) 82865G/82865GV GMCH Datasheet
17
Introduction
Document
Document Number/ Location http://developer.intel.com/ technology/memory/pcsdram/ spec/index.htm http://www.intel.com/ technology/agp/agp_index.htm http://www.ddwg.org/ downloads.html
Intel(R) PC SDRAM Specification Accelerated Graphics Port Interface Specification, Revision 2.0 Digital Visual Interface (DVI) Specification, Revision 1.0
NOTE: For additional related documents, refer to the Intel(R) 865G//865GV865PE/865P Chipset Platform Design Guide.
1.3
Intel(R) 865G Chipset System Overview
Figure 1 shows an example block diagram of an 865G chipset-based platform. The 865G chipset is designed for use in a desktop system based on a Pentium 4 processor with 512-KB L2 cache on 0.13 micron process and the Pentium 4 processor on 90 nm process. The processor interface supports the Pentium 4 processor subset of the Extended Mode of the Scalable Bus Protocol. The GMCH provides the processor interface, system memory interface, CSA interface, AGP interface, hub interface, and additional interfaces. The GMCH contains and integrated graphics device. The 865G chipset platform supports either an integrated graphics device (IGD) or an external graphics device on AGP. The IGD has 3D, 2D, and video capabilities. The IGD also has two multiplexed Intel DVO ports to support DVO devices. The GMCH's AGP interface supports 1X/4X/8X AGP data transfers and 4X/8X AGP Fast Writes, as defined in the Accelerated Graphics Port Interface Specification, Revision 3.0. The GMCH provides a Communications Streaming Architecture (CSA) Interface that connects the GMCH to a Gigabit Ethernet (GbE) controller. The 865G chipset platform supports 4 GB of system memory and has a maximum bandwidth of 6.4 GB/s using DDR400 in dual-channel mode. The 82801EB ICH5 integrates an Ultra ATA 100 controller, two Serial ATA host controllers, one EHCI host controller, and four UHCI host controllers supporting eight external USB 2.0 ports, LPC interface controller, flash BIOS interface controller, PCI interface controller, AC '97 digital controller, integrated LAN controller, an ASF controller and a hub interface for communication with the GMCH. The ICH5 component provides the data buffering and interface arbitration required to ensure that system interfaces operate efficiently and provide the bandwidth necessary to enable the system to obtain peak performance. The 82801ER ICH5R elevates Serial ATA storage performance to the next level with Intel(R) RAID Technology. The ACPI compliant ICH5 platform can support the Full-on, Stop Grant, Suspend to RAM, Suspend to Disk, and Soft-Off power management states. Through the use of the integrated LAN functions, the ICH5 also supports Alert Standard Format for remote management.
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Intel(R) 82865G/82865GV GMCH Datasheet
Introduction
Figure 1. Intel(R) 865G Chipset System Block Diagram
Processor 400/533/800 MHz FSB VGA System Memory Intel (R) 865G Chipset DDR Channel A AGP 8x/ 2 multiplexed DVO ports CSA Interface Gigabit Ethernet 2.1 GB/s Intel(R) 82865G GMCH 2.1 GB/s up to 3.2 GB/s Channel B 2.1 GB/s up to 3.2 GB/s DDR
DDR DDR
266 MB/s 266 MB/s HI 1.5
USB 2.0 8 ports, 480 Mb/s
Power Management Clock Generation
GPIO Intel(R) 82801EB ICH5 or Intel(R) 82801ER ICH5R LAN Connect/ASF System Management (TCO) SMBus 2.0/I2C Six PCI Masters AC '97 3 CODEC support PCI Bus
2 Serial ATA Ports 150 MB/s
2 ATA 100 Ports
Flash BIOS
LPC Interface
SIO
Sys Blk
Intel(R) 82865G/82865GV GMCH Datasheet
19
Introduction
1.4
Intel(R) 82865G GMCH Overview
The GMCH provides the host bridge interfaces and has an integrated graphics device with display interfaces. The GMCH contains advanced desktop power management logic. The GMCH's role in a system is to provide high performance integrated graphics and manage the flow of information between its six interfaces: the processor front side bus (FSB), the memory attached to the SDRAM controller, the AGP 3.0 port, the hub interface, CSA interface, and display interfaces. This includes arbitrating between the six interfaces when each initiates an operation. While doing so, the GMCH supports data coherency via snooping and performs address translation for accesses to the AGP aperture memory. To increase system performance, the GMCH incorporates several queues and a write cache.
1.4.1
Host Interface
The GMCH supports a single, Pentium 4 processor with 512-KB L2 cache on 0.13 micron process. The processor interface supports the Pentium 4 processor subset of the Extended Mode of the Scalable Bus Protocol. The GMCH supports FSB frequencies of 400/533/800 MHz (100 MHz, 133 MHz, and 200 MHz HCLK, respectively) using a scalable FSB VCC_CPU. It supports 32-bit host addressing, decoding up to 4 GB of the processor's memory address space. Host-initiated I/O cycles are decoded to AGP/PCI_B, Hub Interface, or the GMCH configuration space. Host-initiated memory cycles are decoded to AGP/PCI_B, Hub Interface or system memory. All memory accesses from the host interface that hit the graphics aperture are translated using an AGP address translation table. AGP/PCI_B device accesses to non-cacheable system memory are not snooped on the host bus. Memory accesses initiated from AGP/PCI_B using PCI semantics and from hub interface to system SDRAM will be snooped on the host bus.
1.4.2
System Memory Interface
The GMCH integrates a system memory DDR controller with two, 64-bit wide interfaces (up to two channels of DDR). Only Double Data Rate (DDR) SDRAM memory is supported; thus, the buffers support only SSTL_2 signal interfaces. The memory controller interface is fully configurable through a set of control registers.
System Memory Interface
* Supports one or two 64-bit wide DDR data channels * Available bandwidth up to 3.2 GB/s (DDR400) for single-channel mode and 6.4 GB/s * * * * * * * * *
(DDR400) in dual-channel mode. Support for non ECC DIMMs Supports 128-Mb, 256-Mb, 512-Mb DDR technologies Supports only x8, x16, DDR devices with 4-banks Registered DIMMs not supported Supports opportunistic refresh Up to 16 simultaneously open pages (four per row, four rows maximum) SPD (Serial Presence Detect) scheme for DIMM detection support Suspend-to-RAM support using CKE Supports configurations defined in the JEDEC DDR1 DIMM specification only
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Intel(R) 82865G/82865GV GMCH Datasheet
Introduction
Single-Channel DDR Configuration
* * * * * * * * * *
Up to 4.0 GB of DDR Supports up to four DDR DIMMs (2 DIMMs per channel), single-sided and/or double-sided Supports DDR266, DDR333, and DDR400 unregistered non-ECC DIMMs Supports up to 32 simultaneous open pages Does not support mixed-mode / uneven double-sided DDR DIMMs
Dual-Channel DDR Configuration - Lockstep
Up to 4.0 GB of DDR Supports up to four DDR DIMMs, single-sided and/or double-sided DIMMS must be populated in identical pairs for dual-channel operation Supports 16 simultaneous open pages (four per row) Supports DDR266, DDR333, and DDR400 unregistered non-ECC DIMMs
1.4.3
Hub Interface
Communication between the GMCH and the ICH5 occurs over the hub interface. The GMCH supports HI 1.5 that uses HI 1.0 protocol with HI 2.0 electrical characteristics. The hub interface runs at 266 MT/s (with 66 MHz base clock) and uses 1.5 V signaling. Acceses between hub interface and AGP/PCI_B are limited to hub interface-originated memory writes to AGP.
1.4.4
Communications Streaming Architecture (CSA) Interface
The CSA interface connects the GMCH with a Gigabit Ethernet (GbE) controller. The GMCH supports HI 1.5 over the interface that uses HI 1.0 protocol with HI 2.0 electrical characteristics. The CSA interface runs at 266 MT/s (with 66 MHz base clock) and uses 1.5 V signaling.
1.4.5
Multiplexed AGP and Intel(R) DVO Interface
The GMCH multiplexes an AGP interface with two Intel(R) DVOs ports.
AGP Interface
A single AGP or PCI 66 component or connector (not both) is supported by the GMCH's AGP interface. Support for AGP 3.0 includes 0.8 V and 1.5 V AGP electrical characteristics. Support for a single PCI-66 device is limited to the subset supported by the AGP 2.0 specification. An external graphics accelerator is not a requirement due to the GMCH's integrated graphics capabilities. The BIOS will disable the IGD if an external AGP device is detected. The AGP PCI_B buffers operate only in the 1.5 V mode and support the AGP 1.5 V connector. The AGP/PCI_B interface supports up to 8X AGP signaling and up to 8X Fast Writes. AGP semantic cycles to system DDR are not snooped on the host bus. PCI semantic cycles to system DDR are snooped on the host bus. The GMCH supports PIPE# or SBA[7:0] AGP address mechanisms, but not both simultaneously. Either the PIPE# or the SBA[7:0] mechanism must be selected during system initialization. The GMCH contains a 32 deep AGP request queue. Highpriority accesses are supported.
Intel(R) 82865G/82865GV GMCH Datasheet
21
Introduction
DVO Multiplexed Interface
The GMCH supports two multiplexed DVO ports that each drive pixel clocks up to 165 MHz. The DVO ports can each support a single-channel DVO device. If both ports are active in singlechannel mode, they will have identical display timings and data. Alternatively, the DVO ports can be combined to support dual-channel devices that have higher resolutions and refresh rates. The GMCH can make use of these digital display channels via an AGP Digital Display (ADD) card.
1.4.6
Graphics Overview
The GMCH provides an integrated graphics accelerator delivering cost competitive 3D, 2D, and video capabilities. The GMCH contains an extensive set of instructions for 3D operations, BLT and Stretch BLT operations, motion compensation, overlay, and display control. The GMCH's video engines support video conferencing and other video applications. The GMCH does not support a dedicated local graphics memory interface; it may only be used in a UMA configuration. The GMCH also has the capability to support external graphics accelerators via AGP; The IGD cannot work concurrently with an external AGP graphics device. High bandwidth access to data is provided through the system memory port. The GMCH can access local and AGP graphics data located in system memory to 4.2 GB/s (DDR266), 5.4 GB/s (DDR333), or 6.4 GB/s (DDR400) depending on whether single/dual channel memory configuration. The GMCH also provides 2D hardware acceleration for block-level transfers of data (BLTs). The BLT engine provides the ability to copy a source block of data to a destination and perform raster operations (e.g., ROP1, ROP2, and ROP3) on the data using a pattern, and/or another destination. Performing these common tasks in hardware reduces processor load, and thus improves performance. The internal graphics device incorporated in the GMCH is incapable of operating in parallel with an attached AGP device.
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Intel(R) 82865G/82865GV GMCH Datasheet
Introduction
The graphics features on the GMCH include the following:
* Core Frequency of 266 MHz * VGA/UMA Support * High Performance 3D Setup and Render Engine -- Setup matching processor geometry delivery rates -- Triangle Lists, Strips and Fans Support -- Indexed Vertex and Flexible Vertex Formats -- Vertex Cache -- Pixel Accurate Fast Scissoring and Clipping Operation -- Backface Culling Support -- Supports D3D and OGL Pixelization Rules -- Anti-aliased Lines Support -- Sprite Points Support * High-Quality/Performance Texture Engine -- Per Pixel Perspective Corrected Texture Mapping -- Single Pass Quad Texture Compositing -- Enhanced Texture Blending Functions -- 12 Level of Detail MIP Map Sizes from 1x1 to 2Kx2K -- All texture formats including 32-bit RGBA and 8-bit palettes -- Alpha and Luminance Maps -- Texture Color-keying/ChromaKeying -- Bilinear, Trilinear and Anisotropic MIP-Mapped Filtering -- Cubic Environment Reflection Mapping -- Embossed and DOT3 Bump-Mapping -- DXTn Texture Decompression -- FXT1 Texture Compression -- Non-power of 2 Texture -- Render to Texture * 2D Graphics -- Optimized 256-bit BLT Engine -- Alpha Stretch Blitter -- Anti-aliased Lines -- 32-bit Alpha Blended Cursor -- Color Space Conversion -- Programmable 3-Color Transparent Cursor -- 8-, 16- and 32-bit Color -- ROP Support * 3D Graphics Rendering Enhancements -- Flat and Gouraud Shading -- Color Alpha Blending For Transparency -- Vertex and Programmable Pixel Fog and Atmospheric Effects -- Color Specular Lighting -- Z Bias Support -- Dithering -- Line and Full-scene Anti-Aliasied -- 16- and 24-bit Z Buffering -- 16- and 24-bit W Buffering -- 8-bit Stencil Buffering -- Double and Triple Render Buffer Support -- 16- and 32-bit Color -- Destination Alpha -- Vertex Cache -- Maximum 3D Resolution Supported: 1600x1200x32 @ 85Hz -- Fast Clear Support * Video DVD/PC-VCR -- Hardware Motion Compensation for MPEG2 -- Dynamic Bob and Weave Support for Video Streams -- Synclock Display and TV-out to video source -- Source Resolution up to 1280x720 with 3-vertical taps and 1920x1080 with 2-vertical taps -- Software DVD At 30 fps, Full Screen -- Supports 720x480 DVD Quality Encoding at low processor Utilization for PC-VCR or home movie recording and editing -- Video Overlay -- Single High Quality Scalable Overlay -- Multiple Overlay Functionality provided via Stretch Blitter (PIP, Video Conferencing, etc.) -- 5-tap Horizontal, 3-tap Vertical Filtered Scaling -- Independent Gamma Correction -- Independent Brightness/Contrast/Saturation -- Independent Tint/Hue Support -- Destination Color-keying -- Source ChromaKeying -- Maximum Source Resolution: 720x480x32 -- Maximum Overlay Display Resolution: 2048x1536x32 * Video Mixer Render Supported (VMR) * Bi-Cubic Filter Support
Intel(R) 82865G/82865GV GMCH Datasheet
23
Introduction
1.4.7
Display Interface
The GMCH provides interfaces to a progressive scan analog monitor and two DVOs (multiplexed with AGP) capable of driving an ADD card. The digital display channels are capable of driving a variety of DVO devices (e.g., TMDS, LVDS, and TV-Out).
* The GMCH has an integrated 350 MHz RAMDAC that can directly drive a progressive scan
analog monitor up to a resolution of 2048x1536 @ 75Hz.
* The GMCH provides two multiplexed DVOs that are capable of driving a 165 MHz pixel
The GMCH is compliant with DVI Specification 1.0. When combined with a DVI compliant external device and connector, the GMCH has a high-speed interface to a digital display (e.g., flat panel or digital CRT).
clock. It is possible to combine the two multiplexed DVO ports to drive larger digital displays.
1.5
Clock Ratios
Table 2 lists the supported system memory clock ratios. AGP, CSA, and HI run at 66 MHz common clock and are asynchronous to the chipset core. There is no required skew or ratio between FSB/chipset core and 66 MHz system clocks.
Table 2.
System Memory Clock Ratios
Host Clock 100 MHz 133 MHz 200 MHz 133 MHz 200 MHz 200 MHz DRAM Clock 133 MHz 133 MHz 133 MHz 166 MHz 160 MHz 200 MHz Ratios 3/4 1/1 3/2 4/5 5/4 1/1 DRAM Data Rate 266 MT/s 266 MT/s 266 MT/s 333 MT/s 320 MT/s 400 MT/s DRAM Type DDR-DRAM DDR-DRAM DDR-DRAM DDR-DRAM DDR-DRAM DDR-DRAM Peak Bandwidth 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.7 GB/s 2.6 GB/s 3.2 GB/s
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Intel(R) 82865G/82865GV GMCH Datasheet
Signal Description
Signal Description
This chapter provides a detailed description of the GMCH signals. The signals are arranged in functional groups according to their associated interface (see Figure 2).
2
The "#" symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When "#" is not present after the signal name the signal is asserted when at the high voltage level. The following notations are used to describe the signal type: I O I/O s/t/s Input pin Output pin Bi-directional Input/Output pin Sustained Tri-state. This pin is driven to its inactive state prior to tri-stating.
The signal description also includes the type of buffer used for the particular signal: AGTL+ Open Drain AGTL+ interface signal. Refer to the AGTL+ I/O Specification for complete details. The GMCH integrates AGTL+ termination resistors, and supports VTT from 1.15 V to 1.55 V (not including guard banding) AGP interface signals. These signals are compatible with AGP 2.0 1.5 V signaling and AGP 3.0 0.8 V swing signaling Environment DC and AC Specifications. The buffers are not 3.3 V tolerant. Hub Interface 1.5 compatible signals Low Voltage TTL 3.3 V compatible signals Stub Series Terminated Logic 2.6 V compatible signals. 2.6 V buffers used for misc GPIO signals 3.3 V buffers used for DAC/DCC signals CMOS buffers.
AGP
HI15 LVTTL SSTL_2 2.6 VGPIO 3.3 VGPIO CMOS
Host interface signals that perform multiple transfers per clock cycle may be marked as either "4X" (for signals that are "quad-pumped") or 2X (for signals that are "double-pumped"). Note that the processor address and data bus signals are logically inverted signals. In other words, the actual values are inverted from what appears on the processor bus. This has been taken into account in the 865G chipset and the address and data bus signals are inverted inside the GMCH host bridge. All processor control signals follow normal convention. A 0 (zero) indicates an active low level (low voltage) if the signal name is followed by # symbol; a 1 (one) indicates an active high level (high voltage) if the signal has no # suffix.
Intel(R) 82865G/82865GV GMCH Datasheet
25
Signal Description
Figure 2. Intel(R) 82865G GMCH Interface Block Diagram
AGP 2.0 HA[31:3]# HD[63:0]# ADS# BNR# BPRI# DBSY# DEFER# DRDY# HIT# HITM# HLOCK# HREQ[4:0]# HTRDY# RS[2:0]# CPURST# BREQ0# DINV[3:0]# HADSTB[1:0]# HDSTBP[3:0]#, HDSTBN[3:0]# SCS_A[3:0]# SMAA_A[12:0], SMAB_A[5:1] SBA_A[1:0] SRAS_A# SCAS_A# SWE_A# SDQ_A[63:0] SDM_A[7:0] SDQS_A[8:0] SCKE_A[3:0] SCMDCLK_A[5:0], SCMDCLK_A[5:0]# SCS_B[3:0]# SMAA_B[12:0], SMAB_B[5:1] SBA_B[1:0] SRAS_B# SCAS_B# SWE_B# SDQ_B[63:0] SDM_B[7:0] SDQS_B[8:0] SCKE_B[3:0] SCMDCLK_B[5:0], SCMDCLK_B[5:0]# HI[10:0] HISTRS HISTRF CI[10:0] CISTRS CISTRF HCLKP, HCLKN GCLKIN DREFCLK RSTIN# PWROK EXTTS# TESTIN# HSYNC VSYNC RED, RED# GREEN, GREEN# BLUE, BLUE# REFSET DDCA_CLK DDCA_DATA GSBA[7:0] GPIPE# GST[2:0] GRBF# GWBF# GADSTB[1:0], GADSTB[1:0]# GSBSTB, GSBSTB# GFRAME# GIRDY# GTRDY# GSTOP# GDEVSEL# GREQ# GGNT# GAD[31:0] GC/BE[3:0]# GPAR/ADD_DETECT -- DVOB_CLK, DVOB_CLK# DVOB_D[11:0] DVOB_HSYNC DVOB_VSYNC DVOB_BLANK# DVOBC_CLKINT DVOB_FLDSTL DVOC_CLK, DVOC_CLK# DVOC_D[11:0] DVOC_HSYNC DVOC_VSYNC DVOC_BLANK# DVOBC_INTR# DVOC_FLDSTL MI2C_CLK MI2C_DATA MDVI_CLK MDVI_DATA MDDC_CLK MDDC_DATA ADDID[7:0] HDVREF HDRCOMP HDSWING SMVREF_A, SMVREF_B SMXRCOMPVOL, SMYRCOMPVOL SMXRCOMPVOH, SMYRCOMPVOH SMXRCOMP, SMYRCOMP GVREF GVSWING GRCOMP/DVOBCRCOMP HI_VREF HI_RCOMP HI_SWING CI_VREF CI_RCOMP CI_SWING VCC VSS VCCA_AGP VCC_AGP VCCA_FSB VTT VCCA_DPLL VCC_DAC VCCA_DAC VSSA_DAC VCC_DDR VCCA_DDR AGP 3.0 GSBA[7:0]# DBI_HI GST[2:0] GRBF GWBF GADSTBF[1:0], GADSTBS[1:0] GSBSTBF, GSBSTBS GFRAME GIRDY GTRDY GSTOP GDEVSEL GREQ GGNT GAD[31:0] GC#/BE[3:0] GPAR/ADD_DETECT DBI_LO (3.0 only)
Processor System Bus Interface
AGP Interface (multiplexed with DVO)
System Memory DDR Channel A
DVO Device Interface (multiplexed with AGP)
System Memory DDR Channel B
Hub Interface
CSA Interface
Clocks, Reset, & Test
Voltage Refernce, RCOMP, VSW ING, and Power
Analog Display
26
Intel(R) 82865G/82865GV GMCH Datasheet
Signal Description
2.1
Host Interface Signals
Signal Name ADS# Type I/O AGTL+ I/O AGTL+ Description Address Strobe: The processor bus owner asserts ADS# to indicate the first of two cycles of a request phase. The GMCH can assert this signal for snoop cycles and interrupt messages. Block Next Request: BNR# is used to block the current request bus owner from issuing a new requests. This signal is used to dynamically control the processor bus pipeline depth. Priority Agent Bus Request: The GMCH is the only Priority Agent on the processor bus. It asserts this signal to obtain the ownership of the address bus. This signal has priority over symmetric bus requests and will cause the current symmetric owner to stop issuing new transactions unless the HLOCK# signal was asserted. Bus Request 0#: The GMCH pulls the processor bus BREQ0# signal low during CPURST#. The signal is sampled by the processor on the active-to-inactive transition of CPURST#. The minimum setup time for this signal is 4 HCLKs. The minimum hold time is 2 clocks and the maximum hold time is 20 HCLKs. BREQ0# should be terminated high (pulled up) after the hold time requirement has been satisfied. NOTE: This signal is called BR0# in the Intel(R) Pentium(R) 4 processor specifications. Core / FSB Frequency (FSBFREQ) Select Strap: This strap is latched at the rising edge of PWROK. These pins has no default internal pull-up resistor. BSEL[1:0] I CMOS 00 = Core frequency is 100 MHz, FSB frequency is 400 MHz 01 = Core frequency is 133 MHz, FSB frequency is 533 MHz 10 = Core frequency is 200 MHz, FSB frequency is 800 MHz 11 = Reserved CPU Reset: The CPURST# pin is an output from the GMCH. The GMCH asserts CPURST# while RSTIN# (PCIRST# from Intel(R) ICH5) is asserted and for approximately 1 ms after RSTIN# is deasserted. The CPURST# allows the processors to begin execution in a known state. Note that the ICH5 must provide processor frequency select strap setup and hold times around CPURST#. This requires strict synchronization between GMCH CPURST# deassertion and ICH5 driving the straps. Data Bus Busy: This signal is used by the data bus owner to hold the data bus for transfers requiring more than one cycle. Defer: DEFER#, when asserted, indicates that the GMCH will terminate the transaction currently being snooped with either a deferred response or with a retry response. Dynamic Bus Inversion: DINV[3:0]# are driven along with the HD[63:0]# signals. They Indicate if the associated data signals are inverted. DINV[3:0]# are asserted such that the number of data bits driven electrically low (low voltage) within the corresponding 16-bit group never exceeds 8. DINV[3:0]# I/O AGTL+ 4X DINV[x]# DINV3# DINV2# DINV1# DINV0# Data Bits HD[63:48]# HD[47:32]# HD[31:16]# HD[15:0]#
BNR#
BPRI#
O AGTL+
BREQ0#
O AGTL+
CPURST#
O AGTL+
DBSY# DEFER#
I/O AGTL+ O AGTL+
NOTE: This signal is called DBI[3:0] in the processor specifications.
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Signal Description
Signal Name DRDY#
Type I/O AGTL+
Description Data Ready: DRDY# is asserted for each cycle that data is transferred. Host Address Bus: HA[31:3]# connect to the processor address bus. During processor cycles, HA[31:3]# are inputs. The GMCH drives HA[31:3]# during snoop cycles on behalf of HI and AGP/Secondary PCI initiators. HA[31:3]# are transferred at 2X rate. Note that the address is inverted on the processor bus. NOTE: The GMCH drives HA7#, which is then sampled by the processor and the GMCH on the active-to-inactive transition of CPURST#. The minimum setup time for this signal is 4 HCLKs. The minimum hold time is 2 clocks and the maximum hold time is 20 HCLKs. Host Address Strobe: HADSTB[1:0]# are source synchronous strobes used to transfer HA[31:3]# and HREQ[4:0]# at the 2X transfer rate. Strobe HADSTB0# HADSTB1# Address Bits A[16:3]#, REQ[4:0]# A[31:17]#
HA[31:3]#
I/O AGTL+ 2X
HADSTB[1:0]#
I/O AGTL+ 2X I/O AGTL+ 4X
HD[63:0]#
Host Data: These signals are connected to the processor data bus. Data on HD[63:0]# is transferred at a 4X rate. Note that the data signals may be inverted on the processor bus, depending on the DINV[3:0] signals. Differential Host Data Strobes: These signals are differential source synchronous strobes used to transfer HD[63:0]# and DINV[3:0]# at the 4X transfer rate.
HDSTBP[3:0]# HDSTBN[3:0]#
I/O AGTL+ 4X
Strobe HDSTBP3#, HDSTBN3# HDSTBP2#, HDSTBN2# HDSTBP1#, HDSTBN1# HDSTBP0#, HDSTBN0#
Data Bits HD[63:48]#, DINV3# HD[47:32]#, DINV2# HD[31:16]#, DINV1# HD[15:0]#, DINV0#
HIT#
I/O AGTL+ I/O AGTL+ I AGTL+
Hit: This signal indicates that a caching agent holds an unmodified version of the requested line. Hit# is also driven in conjunction with HITM# by the target to extend the snoop window. Hit Modified: This signal indicates that a caching agent holds a modified version of the requested line and that this agent assumes responsibility for providing the line. HITM# is also driven in conjunction with HIT# to extend the snoop window. Host Lock: All processor bus cycles sampled with the assertion of HLOCK# and ADS#, until the negation of HLOCK# must be atomic (i.e., no HI or AGP/PCI snoopable access to system memory are allowed when HLOCK# is asserted by the processor). Host Request Command: These signals define the attributes of the request. HREQ[4:0]# are transferred at 2X rate. They are asserted by the requesting agent during both halves of Request Phase. In the first half of the request phase the signals define the transaction type to a level of detail that is sufficient to begin a snoop request. In the second half the signals carry additional information to define the complete transaction type.
HITM#
HLOCK#
HREQ[4:0]#
I/O AGTL+ 2X
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Intel(R) 82865G/82865GV GMCH Datasheet
Signal Description
Signal Name HTRDY# PROCHOT#
Type O AGTL+ I/0 AGTL+
Description Host Target Ready: This signal indicates that the target of the processor transaction is able to enter the data transfer phase. Processor Hot: This signal informs the chipset when the processor Tj is greater than the thermal Monitor trip point. Response Signals: RS[2:0]# indicate the type of response according to the following: Encoding 000 001 Response Type Idle state Retry response Deferred response Reserved (not driven by GMCH) Hard Failure (not driven by GMCH) No data response Implicit Writeback Normal data response
RS[2:0]#
I/O AGTL+
010 011 100 101 110 111
The following table lists the processor bus interface signals that are not supported by the GMCH.
Signal Name Not Supported AP[1:0]# DP[3:0]# HA[35:32] RSP# IERR# BINIT# MCERR# Function Not Supported Address bus parity Data parity Upper address bits Response (RS) parity Processor Internal Error Bus Initialization Signal Machine Check Error Thus, GMCH Does Not Support Parity protection on address bus Data parity errors on host interface Only supports a 4-GB system address space Response parity errors on host interface Responding to processor internal error Reset of the Host Bus state machines. Signaling or recognition of Machine Check Error
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Signal Description
2.2
2.2.1
Memory Interface
DDR SDRAM Channel A
The following DDR signals are for DDR channel A.
Signal Name Type O SSTL_2 O SSTL_2 O SSTL_2 O SSTL_2 O SSTL_2 O SSTL_2 O SSTL_2 O SSTL_2 O SSTL_2 I/O SSTL_2 O SSTL_2 Description Differential DDR Clock: SCMDCLK_Ax and SCMDCLK_Ax# are differential clock output pairs. The crossing of the positive edge of SCMDCLK_Ax and the negative edge of SCMDCLK_Ax# is used to sample the address and control signals on the SDRAM. There are three pairs to each DIMM. Complementary Differential DDR Clock: These are the complementary Differential DDR Clock signals. Chip Select: These signals select particular SDRAM components during the active state. There is one SCS_Ax# for each SDRAM row, toggled on the positive edge of SCMDCLK_Ax. Memory Address: These signals are used to provide the multiplexed row and column address to the SDRAM. Memory Address Copies: These signals are identical to SMAA_A[5:1] and are used to reduce loading for Selective CPC (clock-per-command). Bank Select (Bank Address): These signals define which banks are selected within each SDRAM row. Bank select and memory address signals combine to address every possible location within an SDRAM device. Row Address Strobe: SRAS_A# is used with SCAS_A# and SWE_A# (along with SCS_A#) to define the SDRAM commands. Column Address Strobe: SCAS_A# is used with SRAS_A# and SWE_A# (along with SCS_A#) to define the SDRAM commands. Write Enable: SWE_A# is used with SCAS_A# and SRAS_A# (along with SCS_A#) to define the SDRAM commands. Data Lines: SDQ_Ax signals interface to the SDRAM data bus. Data Mask: When activated during writes, the corresponding data groups in the SDRAM are masked. There is one SDM_Ax for every eight data lines. SDM_Ax can be sampled on both edges of the data strobes. Data Strobes: Data strobes are used for capturing data. During writes, SDQS_Ax is centered in data. During reads, SDQS_Ax is edge aligned with data. The following lists the data strobe with the data bytes. Data Strobe SDQS_A[7:0] I/O SSTL_2 SDQS_A7 SDQS_A6 SDQS_A5 SDQS_A4 SDQS_A3 SDQS_A2 SDQS_A1 SDQS_A0 Data Byte SDQ_A[63:56] SDQ_A[55:48] SDQ_A[47:40] SDQ_A[39:32] SDQ_A[31:24] SDQ_A[23:16] SDQ_A[15:8] SDQ_A[7:0]
SCMDCLK_A[5:0]
SCMDCLK_A[5:0]# SCS_A[3:0]# SMAA_A[12:0] SMAB_A[5:1]
SBA_A[1:0]
SRAS_A# SCAS_A# SWE_A# SDQ_A[63:0] SDM_A[7:0]
SCKE_A[3:0]
O SSTL_2
Clock Enable: SCKE_A[3:0] are used to initialize DDR SDRAM during power-up and to place all SDRAM rows into and out of self-refresh during Suspend-to-RAM. SCKE_A[3:0] are also used to dynamically power down inactive SDRAM rows. There is one SCKE_Ax per SDRAM row, toggled on the positive edge of SCMDCLK_Ax.
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Intel(R) 82865G/82865GV GMCH Datasheet
Signal Description
2.2.2
DDR SDRAM Channel B
The following DDR signals are for DDR channel B.
Signal Name Type O SSTL_2 O SSTL_2 O SSTL_2 O SSTL_2 O SSTL_2 O SSTL_2 O SSTL_2 O SSTL_2 O SSTL_2 I/O SSTL_2 O SSTL_2 Description Differential DDR Clock: SCMDCLK_Bx and SCMDCLK_Bx# are differential clock output pairs. The crossing of the positive edge of SCMDCLK_Bx and the negative edge of SCMDCLK_Bx# is used to sample the address and control signals on the SDRAM. There are three pairs to each DIMM. Complementary Differential DDR Clock: These are the complementary Differential DDR Clock signals. Chip Select: These signals select particular SDRAM components during the active state. There is one SCS_Bx# for each SDRAM row, toggled on the positive edge of SCMDCLK_Bx. Memory Address: These signals are used to provide the multiplexed row and column address to the SDRAM. Memory Address Copies: These signals are identical to SMAA_B[5:1] and are used to reduce loading for Selective CPC (clock-per-command). Bank Select (Bank Address): These signals define which banks are selected within each SDRAM row. Bank select and memory address signals combine to address every possible location within an SDRAM device. Row Address Strobe: SRAS_B# is used with SCAS_B# and SWE_B# (along with SCS_B#) to define the SDRAM commands. Column Address Strobe: SCAS_B# is used with SRAS_B# and SWE_B# (along with SCS_B#) to define the SDRAM commands. Write Enable: SWE_B# is used with SCAS_B# and SRAS_B# (along with SCS_B#) to define the SDRAM commands. Data Lines: SDQ_B signals interface to the SDRAM data bus. Data Mask: When activated during writes, the corresponding data groups in the SDRAM are masked. There is one SDM_Bx for every eight data lines. SDM_Bx can be sampled on both edges of the data strobes. Data Strobes: Data strobes are used for capturing data. During writes, SDQS_Bx is centered in data. During reads, SDQS_Bx is edge aligned with data. The following list matches the data strobe with the data bytes. Data Strobe SDQS_B[7:0] I/O SSTL_2 SDQS_B7 SDQS_B6 SDQS_B5 SDQS_B4 SDQS_B3 SDQS_B2 SDQS_B1 SDQS_B0 Data Byte SDQ_B[63:56] SDQ_B[55:48] SDQ_B[47:40] SDQ_B[39:32] SDQ_B[31:24] SDQ_B[23:16] SDQ_B[15:8] SDQ_B[7:0]
SCMDCLK_B[5:0]
SCMDCLK_B[5:0]#
SCS_B[3:0]# SMAA_B[12:0] SMAB_B[5:1]
SBA_B[1:0]
SRAS_B# SCAS_B# SWE_B# SDQ_B[63:0] SDM_B[7:0]
SCKE_B[3:0]
O SSTL_2
Clock Enable: SCKE_B[3:0] are used to initialize DDR SDRAM during power-up and to place all SDRAM rows into and out of self-refresh during Suspend-to-RAM. SCKE_B[3:0] are also used to dynamically power down inactive SDRAM rows. There is one SCKE_Bx per SDRAM row, toggled on the positive edge of SCMDCLK_Bx.
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Signal Description
2.3
Hub Interface
Signal Name HI[10:0] HISTRS HISTRF Type I/O sts HI15 I/O sts HI15 I/O sts HI15 Description Packet Data: HI[10:0] are data signals used for hub interface read and write operations. Packet Strobe: HISTRS is one of two differential strobe signals used to transmit or receive packet data over the hub interface. Packet Strobe Complement: HISTRF is one of two differential strobe signals used to transmit or receive packet data over the hub interface.
2.4
Communication Streaming Architecture (CSA) Interface
Signal Name CI[10:0] CISTRS CISTRF Type I/O sts HI15 I/O sts HI15 I/O sts HI15 Description Packet Data: CI[10:0] are data signals used for CI read and write operations. Packet Strobe: CISTRS is one of two differential strobe signals used to transmit or receive packet data over CI. Packet Strobe Complement: CISTRF is one of two differential strobe signals used to transmit or receive packet data over CI.
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Intel(R) 82865G/82865GV GMCH Datasheet
Signal Description
2.5
2.5.1
AGP Interface
AGP Addressing Signals
Signal Name Type Description Pipelined Read: This signal is asserted by the current master to indicate a full width address is to be queued by the target. The master enqueues one request each rising clock edge while GPIPE# is asserted. When GPIPE# is deasserted, no new requests are enqueued across the GAD bus. GPIPE# may be used in AGP 2.0 signaling modes, but is not permitted by the AGP 3.0 specification. When operating in AGP 3.0 signaling mode, GPIPE# is used for DBI_HI. GPIPE# (2.0) DBI_HI (3.0) GPIPE# is a sustained tri-state signal from the master (graphics controller) and is an input to the GMCH. I/O AGP In AGP 3.0 signaling mode this signal is Dynamic Bus Inversion HI. Dynamic Bus Inversion HI: This signal goes along with GAD[31:16] to indicate whether GAD[31:16] must be inverted on the receiving end. * DBI_HI = 0: * DBI_HI = 1: GAD[31:16] are not inverted so receiver may use as is. GAD[31:16] are inverted so receiver must invert before use.
The GADSTBF1 and GADSTBS1 strobes are used with DBI_HI. In AGP 3.0 4X data rate mode dynamic bus inversion is disabled by the GMCH while transmitting (data never inverted and BI_HI driven low); dynamic bus inversion is enabled when receiving data. For 8X data rate, dynamic bus inversion is enabled when transmitting and receiving data. Sideband Address: This bus provides an additional bus to pass address and command to the GMCH from the AGP master. GSBA[7:0] (2.0) GSBA[7:0]# (3.0) I AGP NOTE: In AGP 2.0 signaling mode, when sideband addressing is disabled, these signals are isolated. When sideband addressing is enabled, internal pull-ups are enabled to prevent indeterminate values on them in cases where the Graphics Card may not have its GSBA[7:0] output drivers enabled yet.
NOTES: 1. The table contains two mechanisms to queue requests by the AGP master. Note that the master can only use one mechanism. When GPIPE# is used to queue addresses the master is not allowed to queue addresses using the SB bus. For example, during configuration time, if the master indicates that it can use either mechanism, the configuration software will indicate which mechanism the master will use. Once this choice has been made, the master will continue to use the mechanism selected until the master is reset (and reprogrammed) to use the other mode. This change of modes is not a dynamic mechanism but rather a static decision when the device is first being configured after reset. 2. The term (2.0) following a signal name indicates its function in AGP 2.0 signaling mode (1.5 V swing). 3. The term (3.0) following a signal name indicates its function in AGP 3.0 signaling mode (0.8 V swing).
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Signal Description
2.5.2
AGP Flow Control Signals
Signal Name Type Description Read Buffer Full: This signal indicates if the master is ready to accept previously requested low priority read data. When GRBF(#) is asserted, the GMCH is not allowed to return low priority read data to the AGP master on the first block. GRBF(#) is only sampled at the beginning of a cycle. If the AGP master is always ready to accept return read data, then it is not required to implement this signal. Write Buffer Full: This signal indicates if the master is ready to accept Fast Write data from the GMCH. When GWBF(#) is asserted, the GMCH is not allowed to drive Fast Write data to the AGP master. GWBF(#) is only sampled at the beginning of a cycle. If the AGP master is always ready to accept fast write data, then it is not required to implement this signal. NOTE: 1. The term (2.0) following a signal name indicates its function in AGP 2.0 signaling mode (1.5 V swing). 2. The term (3.0) following a signal name indicates its function in AGP 3.0 signaling mode (0.8 V swing).
GRBF# (2.0) GRBF (3.0)
I AGP
GWBF# (2.0) GWBF (3.0)
I AGP
2.5.3
AGP Status Signals
Signal Name GST[2:0] (2.0) GST[2:0] (3.0) Type O AGP Description Status: These signals provides information from the arbiter to an AGP Master on what it may do. GST[2:0] only have meaning to the master when its GGNT(#) is asserted. When GGNT(#) is deasserted, these signals have no meaning and must be ignored. GST[2:0] are always an output from the GMCH and an input to the master. Encoding Meaning 000 001 010 011 100 101 110 111 Previously requested low priority read data (Async read for AGP 3.0 Signaling mode) is being returned to the master. Previously requested high priority read data is being returned to the master. Reserved in AGP 3.0 signaling mode. The master is to provide low priority write data (Async write for AGP 3.0 signaling mode) for a previously queued write command. The master is to provide high priority write data for a previously queued write command. Reserved in AGP 3.0 signaling mode. Reserved. Reserved. Reserved. The master has been given permission to start a bus transaction. The master may queue AGP requests by asserting GPIPE# (4X signaling mode) or start a PCI transaction by asserting GFRAME(#).
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Intel(R) 82865G/82865GV GMCH Datasheet
Signal Description
2.5.4
AGP Strobes
Signal Name Type Description AD Bus Strobe-0: GADSTB0 provides timing for 4X clocked data on GAD[15:0] and GC/BE[1:0]# in AGP 2.0 signaling mode. The agent that is providing data drives this signal. AD Bus Strobe First-0: In AGP 3.0 signaling mode GADSTBF0 strobes the first and all odd numbered data items with a low-to-high transition. It is used with GAD[15:0] and GC#/BE[1:0]. AD Bus Strobe-0 Complement: GADSTB0# is the differential complement to the GADSTB0 signal. It is used to provide timing for 4X clocked data in AGP 2.0 signaling mode. AD Bus Strobe Second-0: In AGP 3.0 signaling mode GADSTBS0 strobes the second and all even numbered data items with a low-to-high transition. AD Bus Strobe-1: GADSTB1 provides timing for 4X clocked data on GAD[31:16] and GC/BE[3:2]# in AGP 2.0 signaling mode. The agent that is providing data drives this signal. AD Bus Strobe First-1: In AGP 3.0 signaling mode GADSTBF1 strobes the first and all odd numbered data items with a low-to-high transition. It is used with GAD[31:16], GC#/BE[3:2], DBI_HI, and DBI_LO. AD Bus Strobe-1 Complement: GADSTB1# is the differential complement to the GADSTB1 signal. It is used to provide timing for 4X clocked data in AGP 2.0 signaling mode. AD Bus STrobe Second-1: In AGP 3.0 signaling mode GADSTBS1 strobes the second and all even numbered data items with a low-to-high transition. Sideband Strobe: GSBSTB provides timing for 4X clocked data on the GSBA[7:0] bus in AGP 2.0 signaling mode. It is driven by the AGP master after the system has been configured for 4X clocked sideband address delivery. Sideband Strobe First: In AGP 3.0 signaling mode GSBSTBF strobes the first and all odd numbered data items with a low-to-high transition. GSBSTB# (2.0) GSBSTBS (3.0) Sideband Strobe Complement: GSBSTB# is the differential complement to the GSBSTB signal. It is used to provide timing for 4X clocked data in AGP 2.0 signaling mode. Sideband Strobe Second: In AGP 3.0 signaling mode GSBSTBS strobes the second and all even numbered data items with a low-to-high transition.
GADSTB0 (2.0) GADSTBF0 (3.0)
I/O (s/t/s) AGP
GADSTB0# (2.0) GADSTBS0 (3.0)
I/O (s/t/s) AGP
GADSTB1 (2.0) GADSTBF1 (3.0)
I/O (s/t/s) AGP
GADSTB1# (2.0) GADSTBS1 (3.0)
I/O (s/t/s) AGP
GSBSTB (2.0) GSBSTBF (3.0)
I AGP
I AGP
NOTE: 1. The term (2.0) following a signal name indicates its function in AGP 2.0 signaling mode (1.5 V swing). 2. The term (3.0) following a signal name indicates its function in AGP 3.0 signaling mode (0.8 V swing).
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Signal Description
2.5.5
PCI Signals-AGP Semantics
PCI signals are redefined when used in AGP transactions carried using AGP protocol extension. For transactions on the AGP interface carried using the PCI protocol, these signals completely preserve PCI 2.1 semantics. The exact roles of all PCI signals during AGP transactions are defined in the following table.
Signal Name GFRAME# (2.0) GFRAME (3.0) Type I/O s/t/s AGP Description GFRAME(#): This signal is driven by the current master to indicate the beginning and duration of a standard PCI protocol ("frame based") transaction and during fast writes. It is not used, and must be inactive during AGP transactions. GIRDY(#): This signal is used for both GFRAME(#) based and AGP transactions. During AGP transactions, it indicates the AGP compliant master is ready to provide all write data for the current transaction. Once GIRDY(#) is asserted for a write operation, the master is not allowed to insert wait states. The assertion of GIRDY(#) for reads indicates that the master is ready to transfer to a subsequent block (4 clocks) of read data. The master is never allowed to insert a wait state during the initial data transfer (first 4 clocks) of a read transaction. However, it may insert wait states after each 4 clock block is transferred. NOTE: There is no GFRAME(#) - GIRDY(#) relationship for AGP transactions. GTRDY(#): This signal is used for both GFRAME(#) based and AGP transactions. During AGP transactions, it indicates the AGP compliant target is ready to provide read data for the entire transaction (when the transfer size is less than or equal to 4 clocks) or is ready to transfer the initial or subsequent block (4 clocks) of data when the transfer size is greater than 4 clocks. The target is allowed to insert wait states after each block (4 clocks) is transferred on both read and write transactions. GSTOP(#): This signal is used during GFRAME(#) based transactions by the target to request that the master stop the current transaction. GSTOP(#) is Not used during AGP transactions. Device Select: During GFRAME(#) based accesses, GDEVSEL(#) is driven active by the target to indicate that it is responding to the access. GDEVSEL(#) is Not used during AGP transactions. Request: This signal is an output of an AGP device. Used to request access to the bus to initiate a PCI (GFRAME(#)) or AGP(GPIPE(#)) request. GREQ(#) is Not required to initiate an AGP request via SBA. Grant: This signal is an output of the GMCH, either granting the bus to the AGP device to initiate a GFRAME(#) or GPIPE(#) access (in response to GREQ(#) active) or to indicate that data is to be transferred for a previously enqueued AGP transaction. GST[2:0] indicates the purpose of the grant. Address/Data: GAD[31:0] provide the address for GFRAME(#) and GPIPE(#) transactions and the data for all transactions. These signals operate at a 1X data rate for GFRAME(#) based cycles, and operate at the specified channel rate (1X, 4X, or 8X) for AGP data phases and fast write data phases.
GIRDY# (2.0) GIRDY (3.0)
I/O s/t/s AGP
GTRDY# (2.0) GTRDY (3.0)
I/O s/t/s AGP
GSTOP# (2.0) GSTOP (3.0) GDEVSEL# (2.0) GDEVSEL (3.0) GREQ# (2.0) GREQ (3.0) GGNT# (2.0) GGNT (3.0)
I/O s/t/s AGP I/O s/t/s AGP I AGP O AGP
GAD[31:0] (2.0) GAD[31:0] (3.0)
I/O AGP
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Intel(R) 82865G/82865GV GMCH Datasheet
Signal Description
Signal Name GC/BE[3:0]# (2.0) GC#/BE[3:0] (3.0)
Type
Description Command/Byte Enables: These signals provide the command during the address phase of a GFRAME(#) or GPIPE(#) transaction and byte enables during data phases. Byte enables are not used for read data of AGP 1X and 2X and 4X and 8X reads. These signals operate at the same data rate as the GAD[31:0] signals at any given time. Parity: GPAR is not used on AGP transactions. It is used during GFRAME(#) based transactions as defined by the PCI specification. GPAR is not used during fast writes.
I/O AGP
GPAR/ ADD_DETECT
I/O AGP
Add Detect: The GMCH multiplexes an ADD_DETECT signal with the GPAR signal on the AGP bus. This signal acts as a strap and indicates whether the interface is in AGP or DVO mode. The GMCH has an internal pull-up on this signal that will naturally pull it high. If an ADD card is present, the signal will be pulled low on the ADD card and the AGP/DVO multiplex select bit in the GMCHCFG register will be set to DVO mode. Motherboards that do not use an AGP connector should have a pull-down resistor on ADD_DETECT if they have digital display devices connected to the interface. Dynamic Bus Inversion LO: This AGP 3.0 only signal goes along with GAD[15:0] to indicate whether GAD[15:0] must be inverted on the receiving end. * DBI_LO= 0: GAD[15:0] are not inverted so receiver may use as is. * DBI_LO= 1: GAD[15:0] are inverted so receiver must invert before use. The GADSTBF1 and GADSTBS1 strobes are used with the DBI_LO. Dynamic bus inversion is used in AGP 3.0 signaling mode only.
DBI_LO (3.0 only)
I/O AGP
NOTES: 1. PCIRST# from the ICH5 is connected to RSTIN# and is used to reset AGP interface logic in the GMCH. The AGP agent will also typically use PCIRST# provided by the ICH5 as an input to reset its internal logic. 2. LOCK# signal is not supported on the AGP interface (even for PCI operations). 3. The term (2.0) following a signal name indicates its function in AGP 2.0 signaling mode (1.5 V swing). 4. The term (3.0) following a signal name indicates its function in AGP 3.0 signaling mode (0.8 V swing).
2.5.5.1
PCI Pins during PCI Transactions on AGP Interface
PCI signals described in a previous table behave according to PCI 2.1 specifications when used to perform PCI transactions on the AGP interface.
2.5.6
Multiplexed Intel(R) DVOs on AGP
The following signals are multiplexed on the AGP signals.
Signal Name DVOB_CLK; DVOB_CLK# DVOB_D[11:0] DVOB_HSYNC DVOB_VSYNC Type O AGP O AGP O AGP O AGP O AGP Description DVOB Clock Output: These pins provide a differential pair reference clock that can run up to 165 MHz. Care should be taken to be sure that DVOB_CLK is connected to the primary clock receiver of the Intel(R) DVO device. DVOB Data: This data bus is used to drive 12-bit pixel data on each edge of DVOB_CLK(#). This provides 24-bits of data per clock. Horizontal Sync: HSYNC signal for the DVOB interface. The active polarity of the signal is programmable. Vertical Sync: VSYNC signal for the DVOB interface. The active polarity of the signal is programmable. Flicker Blank or Border Period Indication: DVOB_BLANK# is a programmable output pin driven by the GMCH. When programmed as a blank period indication, this pin indicates active pixels excluding the border. When programmed as a border period indication, this pin indicates active pixel including the border pixels.
DVOB_BLANK#
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Signal Description
Signal Name DVOBC_CLKINT
Type I AGP
Description DVOBC Pixel Clock Input/Interrupt: This signal may be selected as the reference input to the dot clock PLL (DPLL) for the multiplexed DVOs. This pin may also be programmed to be an interrupt input for either of the multiplexed DVOs. TV Field and Flat Panel Stall Signal: This input can be programmed to be either a TV Field input from the TV encoder or Stall input from the flat panel. When used as a Field input, it synchronizes the overlay field with the TV encoder field when the overlay is displaying an interleaved source. When used as the Stall input, it indicates that the pixel pipeline should stall one horizontal line. The polarity is programmable for both modes and the input may be disabled completely. DVOC Clock Output: These pins provide a differential pair reference clock that can run up to 165 MHz. Care should be taken to be sure that DVOC_CLK is connected to the primary clock receiver of the DVO device. DVOC Data: This data bus is used to drive 12-bit pixel data on each edge of DVOC_CLK(#). This provides 24-bits of data per clock. Horizontal Sync: HSYNC signal for the DVOC interface. The active polarity of the signal is programmable. Vertical Sync: VSYNC signal for the DVOC interface. The active polarity of the signal is programmable. Flicker Blank or Border Period Indication: DVOC_BLANK# is a programmable output pin driven by the GMCH. When programmed as a blank period indication, this pin indicates active pixels excluding the border. When programmed as a border period indication, this pin indicates active pixel including the border pixels. DVOBC Interrupt: This pin may be used as an interrupt input for either of the multiplexed DVOs. TV Field and Flat Panel Stall Signal: This input can be programmed to be either a TV Field input from the TV encoder or Stall input from the flat panel. When used as a Field input, it synchronizes the overlay field with the TV encoder field when the overlay is displaying an interleaved source. When used as the Stall input, it indicates that the pixel pipeline should stall one horizontal line. The polarity is programmable for both modes and the input may be disabled completely. MI2C_CLK: The specific function is I2C_CLK for a multiplexed digital display. This signal is tri-stated during a hard reset. MI2C_DATA: The specific function is I2C_DATA for a multiplexed digital display. This signal is tri-stated during a hard reset. MDVI_CLK: The specific function is DVI_CLK (DDC) for a multiplexed digital display connector. This signal is tri-stated during a hard reset. MDVI_DATA: The specific function is DVI_DATA (DDC) for a multiplexed digital display connector. This signal is tri-stated during a hard reset. MDDC_CLK: This signal may be used as the DDC_CLK for a secondary multiplexed digital display connector. This signal is tri-stated during a hard reset. MDDC_DATA: This signal may be used as the DDC_Data for a secondary multiplexed digital display connector. This signal is tri-stated during a hard reset. ADD Card ID: These signals will be strapped on the ADD card for SW identification purposes. These signals may need pull-up or pull-down resistors in a DVO down scenario.
DVOB_FLDSTL
I AGP
DVOC_CLK; DVOC_CLK# DVOC_D[11:0] DVOC_HSYNC DVOC_VSYNC
O AGP O AGP O AGP O AGP O AGP I AGP
DVOC_BLANK#
DVOBC_INTR#
DVOC_FLDSTL
I AGP
MI2C_CLK MI2C_DATA MDVI_CLK MDVI_DATA MDDC_CLK
I/O AGP I/O AGP I/O AGP I/O AGP I/O AGP I/O AGP I/O AGP
MDDC_DATA
ADDID[7:0]
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Intel(R) 82865G/82865GV GMCH Datasheet
Signal Description
2.5.7
Intel(R) DVO-to-AGP Pin Mapping
The GMCH multiplexes an ADD_DETECT signal with the GPAR signal on the AGP bus. This signal acts as a strap and indicates whether the interface is in AGP or DVO mode (See ADD_DETECT signal description for further information). GSBA(7:0) act as straps for an ADD_ID. When an ADD card is present, ADD_DETECT = 0 (DVO mode), the ADD_ID register (offset 71408h) will hold a valid ADD PROM ID. Table 3 shows the DVO-to-AGP pin mapping. The AGP signal name column only shows the AGP 2.0 signal names.
Table 3.
Intel(R) DVO-to-AGP Pin Mapping
DVO Signal Name DVOB_D0 DVOB_D1 DVOB_D2 DVOB_D3 DVOB_D4 DVOB_D5 DVOB_D6 DVOB_D7 DVOB_D8 DVOB_D9 DVOB_D10 DVOB_D11 DVOB_CLK DVOB_CLK# DVOB_HSYNC DVOB_VSYNC DVOB_BLANK# DVOBC_CLKINT DVOB_FLDSTL DVOBCRCOMP MI2CCLK MI2CDATA MDVI_CLK AGP Signal Name GAD3 GAD2 GAD5 GAD4 GAD7 GAD6 GAD8 GC/BE0# GAD10 GAD9 GAD12 GAD11 GADSTB0 GADSTB0# GAD0 GAD1 GC/BE1# GAD13 GAD14 AGP_RCOMP GIRDY# GDEVSEL# GTRDY# DVO Signal Name DVOC_D0 DVOC_D1 DVOC_D2 DVOC_D3 DVOC_D4 DVOC_D5 DVOC_D6 DVOC_D7 DVOC_D8 DVOC_D9 DVOC_D10 DVOC_D11 DVOC_CLK DVOC_CLK# DVOC_HSYNC DVOC_VSYNC DVOC_BLANK# DVOBC_INTR# DVOC_FLDSTL ADDID[7:0] MDVI_DATA MDDC_CLK MDDC_DATA AGP Signal Name GAD19 GAD20 GAD21 GAD22 GAD23 GC/BE3# GAD25 GAD24 GAD27 GAD26 GAD29 GAD28 GADSTB1 GADSTB1# GAD17 GAD16 GAD18 GAD30 GAD31 GSBA[7:0] GFRAME# GSTOP# GAD15
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Signal Description
2.6
Analog Display Interface
Signal Name HSYNC Type O 3.3 V GPIO O 3.3 V GPIO O Analog O Analog O Analog O Analog O Analog O Analog I Analog I/O 3.3 V GPIO I/O 3.3 V GPIO Description CRT Horizontal Synchronization: This signal is used as the horizontal sync (polarity is programmable) or "sync interval." This signal may need to be level shifted. CRT Vertical Synchronization: This signal is used as the vertical sync (polarity is programmable). This signal may need to be level shifted. RED Analog Video Output: This signal is a CRT Analog video output from the internal color palette DAC. The DAC is designed for a 37.5 equivalent load on each signal (e.g., 75 resistor on the board, in parallel with a 75 CRT load). RED# Analog Output: This signal is an analog video output from the internal color palette DAC. It is connected to a 37.5 resistor to ground. This signal is used to provide noise immunity. GREEN Analog Video Output: This signal is a CRT Analog video output from the internal color palette DAC. The DAC is designed for a 37.5 equivalent load on each signal (e.g., 75 resistor on the board, in parallel with a 75 CRT load). GREEN# Analog Output: This signal is an analog video output from the internal color palette DAC. It is connected to a 37.5 resistor to ground. This signal is used to provide noise immunity. BLUE Analog Video Output: This signal is a CRT Analog video output from the internal color palette DAC. The DAC is designed for a 37.5 equivalent load on each signal (e.g., 75 resistor on the board, in parallel with a 75 CRT load). BLUE# Analog Output: This signal is an analog video output from the internal color palette DAC. It is connected to a 37.5 resistor to ground. This signal is used to provide noise immunity. Resistor Set: Set point resistor for the internal color palette DAC. A 169 , 1% resistor is required between REFSET and motherboard ground. Analog DDC Clock: Clock signal for the I2C style interface that connects to Analog CRT Display. NOTE: This signal may need to be level shifted to 5 Volts. Analog DDC Data: Data signal for the I2C style interface that connects to Analog CRT Display. NOTE: This signal may need to be level shifted to 5 Volts.
VSYNC
RED
RED#
GREEN
GREEN#
BLUE
BLUE# REFSET
DDCA_CLK
DDCA_DATA
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Intel(R) 82865G/82865GV GMCH Datasheet
Signal Description
2.7
Clocks, Reset, and Miscellaneous Signals
Signal Name HCLKP HCLKN Type I CMOS I LVTTL Description Differential Host Clock In: These pins receive a low voltage differential host clock from the external clock synthesizer. This clock is used by all of the GMCH logic that is in the Host clock domain 0.7 V. 66 MHz Clock In:. This pin receives a 66 MHz clock from the clock synthesizer. This clock is used by AGP/PCI and HI clock domains. NOTE: This clock input is required to be 3.3 V tolerant. DREFCLK I LVTTL Display Clock Input: This pin provides a 48 MHz input clock to the Display PLL that is used for 2D/Video/Flat Panel and DAC. NOTE: This clock input is required to be 3.3 V tolerant. Reset In: When asserted this signal will asynchronously reset the GMCH logic. This signal is connected to the PCIRST# output of the ICH5. All AGP/PCI output and bi-directional signals will also tri-state compliant to PCI Rev 2.0 and 2.1 specifications. This input should have a Schmitt trigger to avoid spurious resets. NOTE: This input needs to be 3.3 V tolerant. PWROK I LVTTL I LVTTL Power OK: When asserted, PWROK is an indication to the GMCH that the core power and GCLKIN have been stable for at least 10 s. External Thermal Sensor Input: Open-Drain signal indicating an Over-Temp condition in the platform. This signal should remains asserted for as long as the Over-temp Condition exists. This input pin can be programmed to activate hardware management of memory reads and writes and/or trigger software interrupts. Test Input. This signal is used in the GMCH XOR test mode. See Chapter 8 for use.
GCLKIN
RSTIN#
I LVTTL
EXTTS#
TESTIN#
I
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Signal Description
2.8
RCOMP, VREF, VSWING Signals
Signal Name HDVREF HDRCOMP HDSWING Type I I/O CMOS I Description Host Data Reference Voltage: This signal is the reference voltage input for the data signals of the Host AGTL+ interface. Host RCOMP: HDRCOMP is used to calibrate the Host AGTL+ I/O buffers. Host Voltage Swing: These signals provide a reference voltage used by the FSB RCOMP circuit. Memory Reference Voltage for Channel A: SMVREF_A is the reference voltage input for system memory Interface. This signal is tied internally to SMVREF_B. Thus, only one of these signals needs to be the SMVREF and the other should be decoupled. Memory RCOMP for Channel A: This signal is used to Calibrate VOL. Memory RCOMP for Channel A: This signal is used to Calibrate VOH. Memory RCOMP for Channel A: This signal is used to calibrate the memory I/O buffers. Memory Reference Voltage for Channel B: SMVREF_B is the reference voltage input for System Memory Interface. This signal is tied internally to SMVREF_A. Thus, only one of these signals needs to be the SMVREF and the other should be decoupled. Memory RCOMP for Channel B: This signal is used to Calibrate VOL. Memory RCOMP for Channel B: This signal is used to Calibrate VOH. Memory RCOMP for Channel B: This signal is used to calibrate the memory I/O buffers. AGP Reference: The reference voltage for the AGP/DVO I/O buffers is 0.75 V. AGP Voltage Swing: This signal provides a reference voltage for GRCOMP in AGP mode. Compensation for AGP/DVOB: This signal is used to calibrate the AGP/ DVO buffers. This signal should be connected to ground through a 43 pullup resistor to VDDQ HI Reference: HI_VREF is the reference voltage input for the hub interface. Compensation for HI: This signal is used to calibrate the hub interface I/O buffers. HI Voltage Swing: This signal provides a reference voltage used by the HI_RCOMP circuit. CSA Reference: CI_VREF is the reference voltage input for the CSA interface. Compensation for CSA: This signal is used to calibrate the CSA I/O buffers. CSA Voltage Swing: This signal provides a reference voltage used by the CI_RCOMP circuit.
SMVREF_A SMXRCOMPVOL SMXRCOMPVOH SMXRCOMP
I I I I/O CMOS I I I I/O CMOS I I I/O CMOS I I/O CMOS I I I/O CMOS I
SMVREF_B SMYRCOMPVOL SMYRCOMPVOH SMYRCOMP GVREF GVSWING GRCOMP/ DVOBCRCOMP HI_VREF HI_RCOMP HI_SWING CI_VREF CI_RCOMP CI_SWING
NOTE: 1. Reference the Intel(R) 865G/865GV/865PE/865P Chipset Platform Design Guide for platform design information.
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Intel(R) 82865G/82865GV GMCH Datasheet
Signal Description
2.9
Power and Ground Signals
Signal Name VCC VSS VCCA_AGP VCC_AGP VCCA_FSB VTT VCCA_DPLL VCC_DAC VCCA_DAC VSSA_DAC VCC_DDR VCCA_DDR VCC Supply: This is the 1.5 V core. Gnd Supply AGP PLL Power VCC for AGP: This value can be either 0.8 V or 1.5 V as the GMCH supports both AGP electrical characteristics. Analog VCC for Host PLL: This 1.5 V supply requires special filtering. Refer to the Intel(R) 865G/865GV/865PE/865P Chipset Platform Design Guide for details. VTT: This is the supply for the FSB. Analog VCC for Display PLL: This 1.5 V supply requires special filtering. Refer to the Intel(R) 865G/865GV/865PE/865P Chipset Platform Design Guide for details. DAC VCC Supply: This signal is the 3.3 V VCC for the DAC. Analog DAC VCC: This is the 1.5 V analog supply for the DAC. Refer to the Intel(R) 865G/ 865GV/865PE/865P Chipset Platform Design Guide for supply requirements. Analog DAC VSS: This supply should go directly to motherboard ground. VCC For DDR: This signal is the 2.6 V supply for system memory. Analog VCC for DDR: This signal is the analog 1.5 V supply for the system memory PLLs. This supply requires special filtering. Refer to the Intel(R) 865G/865GV/865PE/865P Chipset Platform Design Guide for details. Description
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Signal Description
2.10
GMCH Sequencing Requirements
Power Plane and Sequencing Requirements:
* Clock Valid Timing: * GCLKIN must be valid at least 10 s prior to the rising edge of PWROK. * HCLKN/HCLKP must be valid at least 10 s prior to the rising edge of RSTIN#.
There is no DREFCLK timing requirements relative to reset. Figure 3. Intel(R) 865G Chipset System Clock and Reset Requirements
POWER ~100 ms PWROK ~1 ms RSTIN#
10 us min GCLKIN valid
10 us min HCLKN/HCLKP valid
The GMCH uses the rising edge of PWROK to latch straps values. During S3, when power is not valid, the GMCH requires that PWROK de-assert and then re-assert when power is valid so that it can properly re-latch the straps.
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Intel(R) 82865G/82865GV GMCH Datasheet
Signal Description
2.11
2.11.1
Signals Used As Straps
Functional Straps
Signal Name Strap Name Description System Bus IOQ Depth Strap: The value on HA7# is sampled by all processor bus agents, including the GMCH, on the deasserting edge of CPURST#. HA7# FSB IOQ Depth NOTE: For HA7#, the minimum setup time is 4 HCLKs. The minimum hold time is 2 clocks and the maximum hold time is 20 HCLKs. The latched value determines the maximum IOQ depth supported on the processor bus. * 0 (low voltage) = BUS IOQ depth on the bus is 1 * 1 (high voltage) = BUS IOQ depth on the bus is the maximum of 12 AGP Operating Mode Select Strap: This strap selects the operating mode of the AGP signals (controls only AGP I/O muxes): * 0 (low voltage) = ADD Card (2X DVO) * 1 (high voltage) = AGP GPAR/ ADD_DETECT AGP/DVO The ADD_DETECT strap is flow-through while RSTIN# is asserted and latched on the de-asserting edge of RSTIN#. RSTIN# is used to make sure that the AGP card is not driving the GPAR/ADD_DETECT signal when it is latched. NOTE: DVO detection mechanism needs to be switched off in AGP 3.0 mode; otherwise, the GMCH will wake up in DVO mode when GVREF is 0.35 V ID Bit Select Strap: This strap signal is used in flow-through fashion while PWROK is de-asserted and is latched on the asserting edge of PWROK. * 0 (low voltage) = ID bit is set to 0 * 1 (high voltage) = ID bit is set to 1 NOTE: 1. All straps, have internal 8 k pull-ups (HA7# has GTL pull-up) enabled during their sampling window. Therefore, a strap that is not connected or not driven by external logic will be sampled high.
SBA[7:0]
ADD Card ID
2.11.2
Strap Input Signals
Signal Name Type Description Core / FSB Frequency (FSBFREQ) Select Strap: This strap is latched at the rising edge of PWROK. These pins has no default internal pull-up resistor. BSEL[1:0] I CMOS 00 = Core frequency is 100 MHz, FSB frequency is 400 MHz 01 = Core frequency is 133 MHz, FSB frequency is 533 MHz 10 = Core frequency is 200 MHz, FSB frequency is 800 MHz 11 = Reserved
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Signal Description
2.12
Full and Warm Reset States
Figure 4. Full and Warm Reset Waveforms
Intel(R) ICH5 Power
ICH5 PWROK In 1 ms Min ICH5 PCIRST# Out GMCH RSTIN# In 1 ms GMCH CPURST# Out
Write to CF9h
1 ms min
1 ms
GMCH Power
GMCH PWROK In
GMCH Reset State
Unknown
Full Reset
Warm Reset
Running
Warm Reset
Running
All register bits assume their default values during full reset. PCIRST# resets all internal flip flops and state machines (except for a few configuration register bits). A full reset occurs when PCIRST# (GMCH RSTIN#) is asserted and PWROK is deasserted. A warm reset occurs when PCIRST# (GMCH RSTIN#) is asserted and PWROK is also asserted. The following table describes the reset states.
Reset State Full Reset Warm Reset Does Not Occur Normal Operation RSTIN# L L H H PWROK L H L H
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Intel(R) 82865G/82865GV GMCH Datasheet
Register Description
Register Description
3
The GMCH contains two sets of software accessible registers, accessed via the host processor I/O address space:
* Control registers that are I/O mapped into the processor I/O space control access to PCI and *
AGP configuration space. Internal configuration registers residing within the GMCH are partitioned into three logical device register rests ("logical" since they reside within a single physical device). The first register set is dedicated to Host-Hub Interface functionality (controls PCI bus #0 operations including DRAM configuration, other chipset operating parameters, and optional features). The second register block is dedicated to Host-AGP/PCI_B Bridge functions (controls AGP/ PCI_B interface configurations and operating parameters). The third register block is dedicated to the Integrated Graphics Device (IGD).
This configuration scheme is necessary to accommodate the existing and future software configuration model supported by Microsoft where the host bridge functionality will be supported and controlled via dedicated and specific driver and virtual PCI-to-PCI bridge functionality will be supported via standard PCI bus enumeration configuration software. The term "virtual" is used to designate that no real physical embodiment of the PCI-to-PCI bridge functionality exists within the GMCH, but that GMCH's internal configuration register sets are organized in this particular manner to create that impression to the standard configuration software. The GMCH supports PCI configuration space accesses using the mechanism denoted as Configuration Mechanism 1 in the PCI specification. The GMCH internal registers (both I/O mapped and configuration registers) are accessible by the host processor. The registers can be accessed as Byte, Word (16-bit), or DWord (32-bit) quantities, with the exception of CONFIG_ADDRESS which can only be accessed as a DWord. All multi-byte numeric fields use "little-endian" ordering (i.e., lower addresses contain the least significant parts of the field).
3.1
Register Terminology
Term RO R/W R/W/L R/WC R/WO L Description Read Only. If a register is read only, writes to this register have no effect. Read/Write. A register with this attribute can be read and written. Read/Write/Lock. A register with this attribute can be read, written, and Locked. Read/Write Clear. A register bit with this attribute can be read and written. However, a write of a 1 clears (sets to 0) the corresponding bit and a write of a 0 has no effect. Read/Write Once. A register bit with this attribute can be written to only once after power up. After the first write, the bit becomes read only. Lock. A register bit with this attribute becomes Read Only after a lock bit is set. Some of the GMCH registers described in this section contain reserved bits. These bits are labeled "Reserved". Software must deal correctly with fields that are reserved. On reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. On writes, software must ensure that the values of reserved bit positions are preserved. That is, the values of reserved bit positions must first be read, merged with the new values for other bit positions and then written back. Note that software does not need to perform a read-merge-write operation for the Configuration Address (CONFIG_ADDRESS) register.
Reserved Bits
Intel(R) 82865G/82865GV GMCH Datasheet
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Register Description
Term
Description In addition to reserved bits within a register, the GMCH contains address locations in the configuration space of the Host-HI Bridge entity that are marked either "Reserved" or "Intel Reserved". The GMCH responds to accesses to reserved address locations by completing the host cycle. When a reserved register location is read, a zero value is returned. (reserved registers can be 8, 16, or 32 bits in size). Writes to reserved registers have no effect on the GMCH. Caution: Register locations that are marked as "Intel Reserved" must not be modified by system software. Writes to "Intel Reserved" register locations may cause system failure. Reads to "Intel Reserved" register locations may return a nonzero value. Upon a reset, the GMCH sets all of its internal configuration registers to predetermined default states. Some register values at reset are determined by external strapping options. The default state represents the minimum functionality feature set required to successfully bring up the system. Hence, it does not represent the optimal system configuration. It is the responsibility of the system initialization software (usually BIOS) to properly determine the SDRAM configurations, operating parameters and optional system features that are applicable, and to program the GMCH registers accordingly.
Reserved Registers
Default Value upon a Reset
3.2
Platform Configuration Structure
In some previous chipsets, the GMCH and the I/O Controller Hub (ICHx) were physically connected by PCI bus 0. From a configuration standpoint, both components appeared to be on PCI bus 0, which was also the system's primary PCI expansion bus. The GMCH contained two PCI devices while the ICHx bridge was considered one PCI device with multiple functions. In the 865G chipset platform, the configuration structure is significantly different. The GMCH and the ICH5 are physically connected by a hub interface (HI); thus, from a configuration standpoint, HI is logically PCI bus 0. As a result, all devices internal to the GMCH and ICH5 appear to be on PCI bus 0. The system's primary PCI expansion bus is physically attached to ICH5 and, from a configuration perspective, appears to be a hierarchical PCI bus behind a PCI-to-PCI bridge; therefore, it has a programmable PCI Bus number. Note that the primary PCI bus is referred to as PCI_A in this document and is not PCI bus 0 from a configuration standpoint. The AGP appears to system software to be a real PCI bus behind PCI-to-PCI bridges resident as devices on PCI bus 0. The GMCH contains four PCI devices within a single physical component. The configuration registers for the four devices are mapped as devices residing on PCI bus 0.
* Device 0: Host-HI Bridge/DRAM Controller. Logically this appears as a PCI device residing
on PCI bus 0. Physically, Device 0 contains the standard PCI registers, SDRAM registers, the Graphics Aperture controller, configuration for HI, and other GMCH specific registers. on PCI bus 0. Physically, Device 1 contains the standard PCI-to-PCI bridge registers and the standard AGP/PCI configuration registers (including the AGP I/O and memory address mapping). PCI bus 0. Physically, Device 2 contains the configuration registers for 3D, 2D, and display functions. (PCI-to-PCI) bridge device
* Device 1: Host-AGP Bridge. Logically this appears as a "virtual" PCI-to-PCI bridge residing
* Device 2: Integrated Graphics Controller. Logically this appears as a PCI device residing on * Device 3: Communications Streaming Architecture (CSA) Port. Appears as a virtual PCI-CSA * Device 6: Function 0: Overflow Device. The sole purpose of this device is to provide
additional configuration register space for Device 0.
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Intel(R) 82865G/82865GV GMCH Datasheet
Register Description
Table 4 shows the Device # assignment for the various internal GMCH devices. Table 4. Internal GMCH Device Assignment
GMCH Function DRAM Controller/8-bit HI Controller Host-to-AGP Bridge (virtual PCI-to-PCI) Integrated Graphics Controller Intergrated GBE (CSA) Overflow Bus #0, Device # Device 0 Device 1 Device 2 Device 3 Device 6
Logically, the ICH5 appears as multiple PCI devices within a single physical component also residing on PCI bus 0. One of the ICH5 devices is a PCI-to-PCI bridge. Logically, the primary side of the bridge resides on PCI 0 while the secondary side is the standard PCI expansion bus. Note: A physical PCI bus 0 does not exist; HI and the internal devices in the GMCH and ICH5 logically constitute PCI Bus 0 to configuration software.
Figure 5. Conceptual Intel(R) 865G Chipset Platform PCI Configuration Diagram
Processor
Host-AGP Bus 0 Device 1 CSA Bus 0 Device 3
PCI Configuration Window I/O Space
GMCH
Integrated GFX Bus 0 Device 2 DRAM Control/ Hub Interf ace Bus 0 Device 0, 6 Hub Interface Intel(R) ICH5
Hub Interface
LPC Bus 0 Device Fcn 0
Hub Interface - PCI Bridge PBus 0 Fcn 0
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Register Description
3.3
Routing Configuration Accesses
The GMCH supports two bus interfaces: HI and AGP/PCI. PCI configuration cycles are selectively routed to one of these interfaces. The GMCH is responsible for routing PCI configuration cycles to the proper interface. PCI configuration cycles to ICH5 internal devices and Primary PCI (including downstream devices) are routed to the ICH5 via HI. AGP/PCI_B configuration cycles are routed to AGP. The AGP/PCI_B interface is treated as a separate PCI bus from a configuration point of view. Routing of configuration AGP/PCI_B is controlled via the standard PCI-to-PCI bridge mechanism using information contained within the Primary Bus Number, the Secondary Bus Number, and the Subordinate Bus Number registers of the corresponding PCI-to-PCI bridge device. A detailed description of the mechanism for translating processor I/O bus cycles to configuration cycles on one of the buses is described in the following sub-sections.
3.3.1
Standard PCI Bus Configuration Mechanism
The PCI Bus defines a slot based "configuration space" that allows each device to contain up to eight functions with each function containing up to 256, 8-bit configuration registers. The PCI specification defines two bus cycles to access the PCI configuration space: Configuration Read and Configuration Write. Memory and I/O spaces are supported directly by the processor. Configuration space is supported by a mapping mechanism implemented within the GMCH. The PCI 2.3 specification defines the configuration mechanism to access configuration space. The configuration access mechanism uses the CONFIG_ADDRESS register (at I/O address 0CF8h though 0CFBh) and CONFIG_DATA register (at I/O address 0CFCh though 0CFFh). To reference a configuration register a DWord I/O write cycle is used to place a value into CONFIG_ADDRESS that specifies the PCI bus, the device on that bus, the function within the device, and a specific configuration register of the device function being accessed. CONFIG_ADDRESS[31] must be 1 to enable a configuration cycle. CONFIG_DATA then becomes a window into the four bytes of configuration space specified by the contents of CONFIG_ADDRESS. Any read or write to CONFIG_DATA will result in the GMCH translating the CONFIG_ADDRESS into the appropriate configuration cycle. The GMCH is responsible for translating and routing the processor's I/O accesses to the CONFIG_ADDRESS and CONFIG_DATA registers to internal GMCH configuration registers, HI, or AGP/PCI_B.
3.3.2
PCI Bus #0 Configuration Mechanism
The GMCH decodes the Bus Number (bits 23:16) and the Device Number fields of the CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0, the configuration cycle is targeting a PCI Bus 0 device. The Host-HI Bridge entity within the GMCH is hardwired as Device 0 on PCI Bus 0. The Host-AGP/PCI_B Bridge entity within the GMCH is hardwired as Device 1 on PCI Bus 0. Device 6 contains test configuration registers.
3.3.3
Primary PCI and Downstream Configuration Mechanism
If the Bus Number in the CONFIG_ADDRESS is non-zero, and is less than the value in the HostAGP/PCI_B device's Secondary Bus Number register or greater than the value in the Host-AGP/ PCI_B device's Subordinate Bus Number register, the GMCH generates a Type 1 HI Configuration
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Intel(R) 82865G/82865GV GMCH Datasheet
Register Description
Cycle. A[1:0] of the HI request packet for the Type 1 configuration cycle is 01. Bits 31:2 of the CONFIG_ADDRESS register are translated to the A[31:2] field of the HI request packet of the configuration cycle as shown in Figure 7. This HI configuration cycle is sent over HI. If the cycle is forwarded to the ICH5 via HI, the ICH5 compares the non-zero Bus Number with the Secondary Bus Number and Subordinate Bus Number registers of its PCI-to-PCI bridges to determine if the configuration cycle is meant for Primary PCI, one of the ICH5's HIs, or a downstream PCI bus.
3.3.4
AGP/PCI_B Bus Configuration Mechanism
From the chipset configuration perspective, AGP/PCI_B is seen as PCI bus interfaces residing on a Secondary Bus side of the virtual PCI-to-PCI bridges referred to as the GMCH Host-PCI_B/AGP bridge. On the Primary bus side, the virtual PCI-to-PCI bridge is attached to PCI Bus 0. Therefore, the Primary Bus Number register is hardwired to 0. The virtual PCI-to-PCI bridge entity converts Type 1 PCI Bus Configuration cycles on PCI Bus 0 into Type 0 or Type 1 configuration cycles on the AGP/PCI_B interface. Type 1 configuration cycles on PCI Bus 0 that have a Bus Number that matches the Secondary Bus Number of the GMCH's "virtual" Host-to-PCI_B/AGP bridge are translated into Type 0 configuration cycles on the PCI_B/AGP interface. The GMCH decodes the Device Number field [15:11] and assert the appropriate GAD signal as an IDSEL in accordance with the PCI-to-PCI bridge Type 0 configuration mechanism. The remaining address bits are mapped as described in Figure 6.
Figure 6. Configuration Mechanism Type 0 Configuration Address-to-PCI Address Mapping
CONFIG_ADDRESS
31 1 Reserved 24 23 Bus Number 16 15 14 11 10 87 Register Number 2 1 x 0 x Device Number Function #
31
24 23 IDSEL
16 15 Reserved = 0
11 10
87 Register Number
2
1 0
0 0
Function #
AGP GAD[31:0] Address
Table 5.
Configuration Address Decoding
Config Addr AD[15:11] 00000 00001 00010 00011 00100 00101 00110 00111 AGP GAD[31:16] IDSEL 0000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 Config Addr AD[15:11] 01000 01001 01010 01011 01100 01101 01110 01111 1xxxx AGP GAD[31:16] IDSEL 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000
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Register Description
If the Bus Number is non-zero, greater than the value programmed into the Secondary Bus Number register, and less than or equal to the value programmed into the Subordinate Bus Number register, the configuration cycle is targeting a PCI bus downstream of the targeted interface. The GMCH generates a Type 1 PCI configuration cycle on PCI_B/AGP. The address bits are mapped as shown in Figure 7. Figure 7. Configuration Mechanism Type 1 Configuration Address-to-PCI Address Mapping
31 30 CONFIG_ADDRESS 1 24 23 Reserve d 16 15 Bus Number Device Number 11 10 87
21
0 XX
Function Number
Reg. Index
PCI Address AD[31:0] 31
0 24 23
Bus Number 16 15
Device Number
Function Number
Reg. Index 21
01 0
11 10
87
To prepare for mapping of the configuration cycles on AGP/PCI_B, initialization software goes through the following sequence: 1. Scans all devices residing on the PCI Bus 0 using Type 0 configuration accesses. 2. For every device residing at bus 0 that implements PCI-PCI bridge functionality, it will configure the secondary bus of the bridge with the appropriate number and scan further down the hierarchy. This process includes the configuration of the virtual PCI-to-PCI bridges within the GMCH used to map the AGP device's address spaces in a software specific manner. Note: Although initial AGP platform implementations will not support hierarchical buses residing below AGP, this specification still must define this capability to support PCI-66 compatibility. Note also that future implementations of the AGP devices may support hierarchical PCI or AGP-like buses coming out of the root AGP device.
3.4
I/O Mapped Registers
The GMCH contains two registers that reside in the processor I/O address space: the Configuration Address (CONFIG_ADDRESS) register and the Configuration Data (CONFIG_DATA) register. The Configuration Address register enables/disables the configuration space and determines what portion of configuration space is visible through the Configuration Data window.
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Register Description
3.4.1
CONFIG_ADDRESS--Configuration Address Register
I/O Address: Default Value: Access: Size: 0CF8h-0CFBh (Accessed as a DWord) 00000000h R/W 32 bits
CONFIG_ADDRESS is a 32-bit register that can be accessed only as a DWord. A Byte or Word reference will "pass through" the Configuration Address register and HI onto the PCI_A bus as an I/O cycle. The CONFIG_ADDRESS register contains the Bus Number, Device Number, Function Number, and Register Number for which a subsequent configuration access is intended.
Bit Configuration Enable (CFGE). 31 30:24 1 = Enable 0 = Disable Reserved. These bits are read only and have a value of 0. Bus Number. When the Bus Number is programmed to 00h, the target of the configuration cycle is a HI agent (GMCH, ICH5, etc.). The configuration cycle is forwarded to HI if the Bus Number is programmed to 00h and the GMCH is not the target (i.e., the device number is not equal to 0, 1, 2, 3, 6 or 7). 23:16 If the Bus Number is non-zero and matches the value programmed into the Secondary Bus Number register of Device 1, a Type 0 PCI configuration cycle will be generated on AGP/PCI_B. If the Bus Number is non-zero, greater than the value in the Secondary Bus Number register of Device 1 and less than or equal to the value programmed into the Subordinate Bus Number register of Device 1, a Type 1 PCI configuration cycle will be generated on AGP/PCI_B. If the Bus Number is non-zero, and does not fall within the ranges enumerated by Device 1's Secondary Bus Number or Subordinate Bus Number register, then a HI Type 1 configuration cycle is generated. Device Number. This field selects one agent on the PCI bus selected by the Bus Number. When the Bus Number field is 00, the GMCH decodes the Device Number field. The GMCH is always Device Number 0 for the Host-HI bridge entity and Device Number 1 for the Host-PCI_B/AGP entity. Therefore, when the Bus Number = 0 and the Device Number equals 0,1, 2, 3, 6, the internal GMCH devices are selected. If the Bus Number is non-zero and matches the value programmed into the Device1 Secondary Bus Number register, a Type 0 PCI configuration cycle is generated on AGP/PCI_B. The Device Number field is decoded and the GMCH asserts one and only one GADxx signal as an IDSEL. GAD16 is asserted to access Device 0, GAD17 for Device 1, and so forth up to Device 15 for which will assert AD31. All device numbers higher than 15 cause a type 0 configuration access with no IDSEL asserted; this will result in a Master Abort reported in the GMCH's virtual PCI-to-PCI bridge registers. For Bus Numbers resulting in HI configuration cycles, the GMCH propagates the Device Number field as A[15:11]. For Bus Numbers resulting in AGP/PCI_B Type 1 configuration cycles, the Device Number is propagated as GAD[15:11]. 10:8 Function Number. This field is mapped to GAD[10:8] during AGP/PCI_B configuration cycles and A[10:8] during HI configuration cycles. This allows the configuration registers of a particular function in a multi-function device to be accessed. The GMCH ignores configuration cycles to its internal devices if the function number is not equal to 0. Register Number. This field selects one register within a particular bus, device, and function as specified by the other fields in the Configuration Address register. This field is mapped to GAD[7:2] during AGP/PCI_B Configuration cycles and A[7:2] during HI configuration cycles. Reserved. These bits are read only. Descriptions
15:11
7:2 1:0
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Register Description
3.4.2
CONFIG_DATA--Configuration Data Register
I/O Address: Default Value: Access: Size: 0CFCh-0CFFh 00000000h R/W 32 bits
CONFIG_DATA is a 32-bit read/write window into configuration space. The portion of configuration space that is referenced by CONFIG_DATA is determined by the contents of CONFIG_ADDRESS.
Bit 31:0 Descriptions Configuration Data Window (CDW). If bit 31 of CONFIG_ADDRESS is 1, any I/O access to CONFIG_DATA are mapped to configuration space using the contents of CONFIG_ADDRESS.
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Register Description
3.5
DRAM Controller/Host-Hub Interface Device Registers (Device 0)
This section contains the DRAM Controller and Host-Hub Interface PCI configuration registers listed in order of ascending offset address. The register address map is shown in Table 6.
Table 6.
DRAM Controller/Host-Hub Interface Device Register Address Map (Device 0) (Sheet 1 of 2)
Address Offset 00-01h 02-03h 04-05h 06-07h 08h 09h 0Ah 0Bh 0C 0Dh 0Eh 0Fh 10-13h 14-2Bh 2C-2Dh 2E-2Fh 30-33h 34h 35-50h 51h 52h 53h 54-5Fh 60h 61-89h 90h 91h 92h 93h 94h Register Symbol VID DID PCICMD PCISTS RID -- SUBC BCC -- MLT HDR -- APBASE -- SVID SID -- CAPPTR -- AGPM GC CSABCONT -- FPLLCONT -- PAM0 PAM1 PAM2 PAM3 PAM4 Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Intel Reserved Sub-Class Code Base Class Code Intel Reserved Master Latency Timer Header Type Intel Reserved Aperture Base Configuration Intel Reserved Subsystem Vendor Identification Subsystem Identification Intel Reserved Capabilities Pointer Intel Reserved AGP Miscellaneous Configuration Graphics Control CSA Basic Control Intel Reserved FPLL Clock Control Intel Reserved Programmable Attribute Map 0 Programmable Attribute Map 1 Programmable Attribute Map 2 Programmable Attribute Map 3 Programmable Attribute Map 4 Default Value 8086h 2570h 0006h 0090h See register description -- 00h 06h -- 00h 00h -- 00000008h -- 0000h 0000h -- E4h -- 00h 0000_1000b 00h -- 00h -- 00h 00h 00h 00h 00h Access RO RO RO, R/W RO, R/WC RO -- RO RO -- RO RO -- RO, R/W -- R/WO R/WO -- RO RO R/W R/W RO, R/W -- R/W, RO -- RO, R/W RO, R/W RO, R/W RO, R/W RO, R/W
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Register Description
Table 6.
DRAM Controller/Host-Hub Interface Device Register Address Map (Device 0) (Sheet 2 of 2)
Address Offset 95h 96h 97h 98-9Ch 9Dh 9Eh 9Fh A0-A3h A4-A7h A8-ABh AC-AFh B0-B3h B4h B5-B7h B8-BBh BCh BDh BE-C3h C4-C5h C6-C7h C8-C9h CA-CEh CF-DDh DE-DFh E0-E3h E4-E8h E9-FFh Register Symbol PAM5 PAM6 FDHC -- SMRAM ESMRAMC -- ACAPID AGPSTAT AGPCMD -- AGPCTRL APSIZE -- ATTBASE AMTT LPTT -- TOUD GMCHCFG ERRSTS ERRCMD -- SKPD -- CAPREG -- Register Name Programmable Attribute Map 5 Programmable Attribute Map 6 Fixed SDRAM Hole Control Intel Reserved System Management RAM Control Extended System Management RAM Control Intel Reserved AGP Capability Identifier AGP Status AGP Command Intel Reserved AGP Control Aperture Size Intel Reserved Aperture Translation Table AGP MTT Control AGP Low Priority Transaction Timer Intel Reserved Top of Used DRAM GMCH Configuration Error Status Error Command Intel Reserved Scratchpad Data Intel Reserved Capability Identification Intel Reserved Default Value 00h 00h 00h -- 02h 38h -- 00300002h See register description See register description -- 0000 0000h 00h -- 00000000h 10h 10h -- 0400h 0000h 0000h 0000h -- 0000h -- FF_F104_A009h -- Access RO, R/W RO, R/W RO, R/W -- RO, R/W, L RO, R/W, RWC, L -- RO RO RO, R/W -- RO, R/W RO, R/W -- R/W RO, R/W R/W -- RO, R/W R/WO, RO, R/W R/WC RO, R/W -- R/W -- RO --
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Register Description
3.5.1
VID--Vendor Identification Register (Device 0)
Address Offset: Default Value: Access: Size: 00-01h 8086h RO 16 bits
The VID register contains the vendor identification number. This 16-bit register, combined with the Device Identification register, uniquely identifies any PCI device.
Bit 15:0 Descriptions Vendor Identification (VID)--RO. This register field contains the PCI standard identification for Intel, 8086h.
3.5.2
DID--Device Identification Register (Device 0)
Address Offset: Default Value: Access: Size: 02-03h 2570h RO 16 bits
This 16-bit register, combined with the Vendor Identification register, uniquely identifies any PCI device.
Bit 15:0 Descriptions Device Identification Number (DID)--RO. This is a 16-bit value assigned to the GMCH Host-HI Bridge Function 0.
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Register Description
3.5.3
PCICMD--PCI Command Register (Device 0)
Address Offset: Default Value: Access: Size: 04-05h 0006h RO, R/W 16 bits
Since GMCH Device 0 does not physically reside on PCI_A, many of the bits are not implemented. Writes to non-implemented bits have no effect.
Bit 15:10 9 Reserved. Fast Back-to-Back Enable (FB2B)--RO. Hardwired to 0. This bit controls whether or not the master can do fast back-to-back writes. Since Device 0 is strictly a target, this bit is not implemented and is hardwired to 0. SERR Enable (SERRE)--R/W. This bit is a global enable bit for Device 0 SERR messaging. The GMCH does not have a SERR signal. The GMCH communicates the SERR condition by sending a SERR message over HI to the ICH5. 8 0 = Disable. The SERR message is not generated by the GMCH for Device 0. Note that this bit only controls SERR messaging for the Device 0. Device 1 has its own SERRE bits to control error reporting for error conditions occurring on their respective devices. The control bits are used in a logical OR manner to enable the SERR HI message mechanism. 1 = Enable. The GMCH is enabled to generate SERR messages over HI for specific Device 0 error conditions that are individually enabled in the ERRCMD register. The error status is reported in the ERRSTS and PCISTS registers. Address/Data Stepping Enable (ADSTEP)--RO. Hardwired to 0. Parity Error Enable (PERRE)--RO. Hardwired to 0. The PERR# signal is not implemented by the GMCH. VGA Palette Snoop Enable (VGASNOOP)--RO. Hardwired to 0. Memory Write and Invalidate Enable (MWIE)--RO. Hardwired to 0. The GMCH will never issue memory write and invalidate commands. Special Cycle Enable (SCE)--RO. Not implemented; hardwired to 0. Bus Master Enable (BME)--RO. Hardwired to 1. GMCH is always enabled as a master on HI. Memory Access Enable (MAE)--RO. Hardwired to 1. The GMCH always allows access to main memory. I/O Access Enable (IOAE)--RO. Hardwired to 0. Descriptions
7 6 5 4 3 2 1 0
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Register Description
3.5.4
PCISTS--PCI Status Register (Device 0)
Address Offset: Default Value: Access: Size: 06-07h 0090h RO, R/WC 16 bits
PCISTS is a 16-bit status register that reports the occurrence of error events on Device 0's PCI interface. Since GMCH Device 0 does not physically reside on PCI_A, many of the bits are not implemented.
Bit 15 Descriptions Detected Parity Error (DPE)--RO. Hardwired to 0. Signaled System Error (SSE)--R/WC. 14 0 = Software sets this bit to 0 by writing a 1 to it. 1 = GMCH Device 0 generated a SERR message over HI for any enabled Device 0 error condition. Device 0 error conditions are enabled in the PCICMD and ERRCMD registers. Device 0 error flags are read/reset from the PCISTS or ERRSTS registers. Received Master Abort Status (RMAS)--R/WC. 13 0 = Software sets this bit to 0 by writing a 1 to it. 1 = GMCH generated a HI request that receives a Master Abort completion packet or Master Abort Special Cycle. Received Target Abort Status (RTAS)--R/WC. 12 0 = Software sets this bit to 0 by writing a 1 to it. 1 = GMCH generated a HI request that receives a Target Abort completion packet or Target Abort Special Cycle. Signaled Target Abort Status (STAS)--RO. Hardwired to 0. The GMCH will not generate a Target Abort HI completion packet or Special Cycle. DEVSEL Timing (DEVT)--RO. Hardwired to 00. Device 0 does not physically connect to PCI_A. These bits are set to 00 (fast decode) so that optimum DEVSEL timing for PCI_A is not limited by the GMCH. Master Data Parity Error Detected (DPD)--RO. Hardwired to 0. PERR signaling and messaging are not implemented by the GMCH. Fast Back-to-Back (FB2B)--RO. Hardwired to 1. Device 0 does not physically connect to PCI_A. This bit is set to 1 (indicating fast back-to-back capability) so that the optimum setting for PCI_A is not limited by the GMCH. Reserved. Capability List (CLIST)--RO. Hardwired to 1. A 1 indicates to the configuration software that this device/function implements a list of new capabilities. A list of new capabilities is accessed via register CAPPTR at configuration address offset 34h. Register CAPPTR contains an offset pointing to the start address within configuration space of this device where the AGP Capability standard register resides. Reserved.
11 10:9 8 7 6:5
4
3:0
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Register Description
3.5.5
RID--Revision Identification Register (Device 0)
Address Offset: Default Value: Access: Size: 08h See table below RO 8 bits
This register contains the revision number of the GMCH Device 0.
Bit 7:0 Descriptions Revision Identification Number (RID)--RO. This is an 8-bit value that indicates the revision identification number for the GMCH Device 0. 02h = A-2 stepping
3.5.6
SUBC--Sub-Class Code Register (Device 0)
Address Offset: Default Value: Access: Size: 0Ah 00h RO 8 bits
This register contains the Sub-Class Code for the GMCH Device 0.
Bit 7:0 Descriptions Sub-Class Code (SUBC)--RO. This is an 8-bit value that indicates the category of bridge for the GMCH. 00h = Host bridge.
3.5.7
BCC--Base Class Code Register (Device 0)
Address Offset: Default Value: Access: Size: 0Bh 06h RO 8 bits
This register contains the Base Class Code of the GMCH Device 0.
Bit 7:0 Descriptions Base Class Code (BASEC)--RO. This is an 8-bit value that indicates the Base Class Code for the GMCH. 06h = Bridge device.
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Register Description
3.5.8
MLT--Master Latency Timer Register (Device 0)
Address Offset: Default Value: Access: Size: 0Dh 00h RO 8 bits
Device 0 in the GMCH is not a PCI master. Therefore, this register is not implemented.
Bit 7:0 Reserved. Descriptions
3.5.9
HDR--Header Type Register (Device 0)
Address Offset: Default Value: Access: Size: 0Eh 00h RO 8 bits
This register identifies the header layout of the configuration space. No physical register exists at this location.
Bit 7:0 Descriptions PCI Header (HDR)--RO. This field always returns 0 to indicate that the GMCH is a single function device with standard header layout.
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Register Description
3.5.10
APBASE--Aperture Base Configuration Register (Device 0)
Address Offset: Default Value: Access: Size: 10-13h 00000008h RO, R/W 32 bits
The APBASE is a standard PCI base address register that is used to set the base of the graphics aperture. The standard PCI Configuration mechanism defines the base address configuration register such that only a fixed amount of space can be requested (dependent on which bits are hardwired to 0 or behave as hardwired to 0). To allow for flexibility (of the aperture) an additional register called APSIZE is used as a "back-end" register to control which bits of the APBASE will behave as hardwired to 0. This register will be programmed by the GMCH specific BIOS code that will run before any of the generic configuration software is run. Note: Bit 1 of the AGPM register is used to prevent accesses to the aperture range before this register is initialized by the configuration software and the appropriate translation table structure has been established in the main memory.
Bit Descriptions Upper Programmable Base Address (UPBITS)--R/W. These bits are part of the aperture base set by configuration software to locate the base address of the graphics aperture. They correspond to bits [31:28] of the base address in the processor's address space that will cause a graphics aperture translation to be inserted into the path of any memory read or write. Middle Hardwired/Programmable Base Address (MIDBITS)--R/W. These bits are part of the aperture base set by configuration software to locate the base address of the graphics aperture. They correspond to bits [27:4] of the base address in the processor's address space that cause a graphics aperture translation to be inserted into the path of any memory read or write. These bits can behave as though they were hardwired to 0 if programmed to do so by the APSIZE bits of the APSIZE register. This causes configuration software to understand that the granularity of the graphics aperture base address is either finer or more coarse, depending upon the bits set by GMCH-specific configuration software in APSIZE. Lower Bits (LOWBITS)--RO. Hardwired to 0s. This forces the minimum aperture size selectable by this register to be 4 MB, without regard to the aperture size definition enforced by the APSIZE register. Prefetchable (PF)--RO. Hardwired to 1 to identify the graphics aperture range as a prefetchable as per the PCI specification for base address registers. This implies that there are no side effects on reads, the device returns all bytes on reads regardless of the byte enables, and the GMCH may merge processor writes into this range without causing errors. Addressing Type (TYPE)--RO. Hardwired to 00 to indicate that address range defined by the upper bits of this register can be located anywhere in the 32-bit address space as per the PCI specification for base address registers. Memory Space Indicator (MSPACE)--RO. Hardwired to 0 to identify the aperture range as a memory range as per the specification for PCI base address registers.
31:28
27:22
21:4
3
2:1 0
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Register Description
3.5.11
SVID--Subsystem Vendor Identification Register (Device 0)
Address Offset: Default Value: Access: Size: 2C-2Dh 0000h R/WO 16 bits
This value is used to identify the vendor of the subsystem.
Bit 15:0 Descriptions Subsystem Vendor ID (SUBVID)--R/WO. This field should be programmed during boot-up to indicate the vendor of the system board. After it has been written once, it becomes read only.
3.5.12
SID--Subsystem Identification Register (Device 0)
Address Offset: Default Value: Access: Size: 2E-2Fh 0000h R/WO 16 bits
This value is used to identify a particular subsystem.
Bit 15:0 Descriptions Subsystem ID (SUBID)--R/WO. This field should be programmed during BIOS initialization. After it has been written once, it becomes read only.
3.5.13
CAPPTR--Capabilities Pointer Register (Device 0)
Address Offset: Default Value: Access: Size: 34h E4h RO 8 bits
The CAPPTR provides the offset that is the pointer to the location of the first device capability in the capability list.
Bit 7:0 Descriptions Capabilities Pointer Address-- RO. This field contains the pointer to the offset of the first capability ID register block. In this case the first capability is the Product-Specific Capability, which is located at offset E4h.
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Register Description
3.5.14
AGPM--AGP Miscellaneous Configuration Register (Device 0)
Address Offset: Default Value: Access: Size: 51h 00h R/W 8 bits
Bit 7:2 Reserved.
Descriptions
1
Aperture Access Global Enable (APEN)--R/W. This bit is used to prevent access to the graphics aperture from any port (processor, HI, or AGP/PCI_B) before the aperture range is established by the configuration software and the appropriate translation table in the main SDRAM has been initialized. 0 = Disable.The default value is 0, so this field must be set after system is fully configured to enable aperture accesses. 1 = Enable.
0
Reserved.
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Register Description
3.5.15
GC--Graphics Control Register (Device 0)
Address Offset: Default Value: Access: Size:
Bit 7 Reserved Graphics Mode Select (GMS)--R/W/L. This field is used to select the amount of main memory that is pre-allocated to support the Internal Graphics device in VGA (non-linear) and Native (linear) modes. The BIOS ensures that memory is pre-allocated only when Internal graphics is enabled. 000 = No memory pre-allocated. Device 2 (IGD) does not claim VGA cycles (Memory and I/O), and the Sub-Class Code field within Device 2 function 0 Class Code register is 80. (Default) 001 = DVMT (UMA) mode:1 MB of memory pre-allocated for frame buffer. 010 = Reserved 6:4 011 = DVMT (UMA) mode:8 MB of memory pre-allocated for frame buffer. 100 = DVMT (UMA) mode:16 MB of memory pre-allocated for frame buffer. 101 =Reserved 110 = Reserved 111 = Reserved NOTE: These register bits are locked and becomes Read Only when the D_LCK bit in the SMRAM register is set. Integrated Graphics Disable (IGDIS)--R/W. 0 = IGD Enable. When this bit is 0, the GMCH's Device 1 is disabled such that all configuration cycles to Device 1 flow through to HI. Also, the Next_Pointer field in the CAPREG register (Dev 0, Offset E4h) will be RO at A0h. 1 = IGD is disabled and AGP Graphics is enabled (default). The GMCH's Device 2 and associated spaces are disabled; all configuration cycles to Device 2 flow through to HI. NOTE: When writing a new value to this bit, software must perform a clock synchronization sequence. 2 Reserved IGD VGA Disable (IVD)--R/W. 1 0 = IGD claims VGA memory and I/O cycles; the Sub-Class Code within Device 2 Class Code register is 00h. (Default) 1 = IGD does not claim VGA cycles (Memory and I/O); the Sub-Class Code field within Device 2 Class Code register is 80h. Reserved
52h 0000_1000h R/W, R/W/L 8 bits
Descriptions
3
0
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Register Description
Notes on Pre-Allocated Memory for Graphics
These register bits control the use of memory from main memory space as graphics local memory. The memory for TSEG is pre-allocated first and then the graphics local memory is pre-allocated. An example of this theft mechanism is: TOUD equals 62.5 MB = 03E7FFFFh TSEG selected as 512 KB in size, Graphics local memory selected as 1 MB in size General System RAM available in system = 62.5 MB General system RAM range00000000h to 03E7FFFFh TSEG address range03F80000h to 03FFFFFFh TSEG pre-allocated from03F80000h to 03FFFFFFh Graphics local memory pre-allocated from03E80000h to 03F7FFFFh
VGA Memory and I/O Space Decode Priority
1. Integrated Graphics Device (IGD), Device 2. 2. PCI-to-PCI bridge, Device 1. 3. Hub Interface.
VGA Memory Space Decode to IGD
IF IGE = 1 AND IVD = 0 AND Device 2 Mem_Access_En = 1 AND Device 2 in powered up D0 state AND
AND MSRb1 = 1
Additional qualification within IGD decode (comprehends MDA requirements)
Mem Access GR06(3:2) 00 01 10 11 A0000h-AFFFFh IGD IGD PCI-to-PCI Bridge or Hub Interface PCI-to-PCI Bridge or Hub Interface B0000h-B7FFFh IGD PCI-to-PCI Bridge or Hub Interface IGD PCI-to-PCI Bridge or Hub Interface B8000h-BFFFFh IGD PCI-to-PCI Bridge or Hub Interface PCI-to-PCI Bridge or Hub Interface IGD
ELSE VGA Mem space legacy decode: IF Device 1 Mem_Access_En = 1. VGA Mem Range MDA Mem Range
VGA_en 0 0 1 1 MDAP 0 1 0 1
xA0000h - xBFFFFh xB0000h - xB7FFFh
Range VGA, MDA Illegal VGA, MDA VGA, MDA Destination Hub Interface Illegal AGP AGP, Hub Interface Illegal Exceptions/Notes
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Intel(R) 82865G/82865GV GMCH Datasheet
Register Description
ELSE defaults to Hub Interface. VGA IO space decode to IGD: IF IGE = 1 AND IVD = 0 AND Device 2 IO_Access_En = 1 AND Device 2 in Powered up D0 state AND Additional qualification within IGD decode (comprehends MDA requirements).
IO Access MSRb0 0 1 3CX IGD IGD 3DX PCI-to-PCI Bridge or Hub Interface IGD 3B0h-3BBh IGD PCI-to-PCI Bridge or Hub Interface 3BCh-3BFh PCI-to-PCI Bridge or Hub Interface PCI-to-PCI Bridge or Hub Interface
ELSE VGA IO space Legacy Decode: IF Device 1 IO_Access_En = 1. VGA I/O MDA I/O
VGA_EN 0 0 1 1
x3B0h - x3BBh and x3C0h - x3DFh x3B4h, x3B5h, x3B8h, x3B9h, x3BAh, x3BFh
MDAP 0 1 0 1 Range VGA, MDA Illegal VGA VGA, MDA Destination Hub Interface Illegal AGP AGP Hub Interface Exceptions/Notes x3BCh - x3BFh goes to AGP if ISA enabled bit is not set in Device 1 Illegal Non-VGA Ranges will also go to Hub Interface x3BCh - x3BEh will also go to Hub Interface
ELSE defaults to Hub Interface.
3.5.16
CSABCONT--CSA Basic Control Register (Device 0)
Address Offset: Default: Access: Size:
Bit 7:1 0 Reserved. Device Not Present bit--R/W. 0 = Device Not Enabled 1 = Device Enabled
53h 00h R/W, RO 8 bits
Description
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Register Description
3.5.17
FPLLCONT-- Front Side Bus PLL Clock Control Register (Device 0)
Address Offset: Default Value: Access: Size: 60h 00h R/W, RO 8 bits
These register bits are used for changing DDR frequency initializing GMCH memory and I/O clocks WIO DLL delays, and initializing internal graphics controller's clocks and resets.
Bit 7:5 Reserved. Memory and Memory I/O DLL Clock Gate (DLLCKGATE)--R/W. 4 0 = Writing a 0 will cleanly re-enable the memory and memory I/O clocks from the DLL outputs. 1 = Writing a 1 will cleanly disable the memory and memory IO clocks of the chipset core and DDR interface from the DLL outputs. NOTE: This bit should always be written to before writing to the FPLLSYNC bit. Graphics Activate (GFXACT)--R/W. 1 = After propagating the internal graphics enable, writing a 1 to this bit will cause the internal graphics logic to come out of reset. After a 1 has been written, the GMCH will take the internal graphics logic out of reset. From then on, the internal graphics can only be put back into reset with a hardware reset. Propagate Internal Graphics Enable (PIGE)--R/W. 2 0 = This bit should be set to 0 shortly after setting it to 1, though no action is taken on writing a 0. 1 = After writing a 0 to IGDIS (Dev 0, Offset 52, bit 3) to enable internal graphics, writing a 1 to this bit will propagate the IGDIS register to the chip which will make the configuration space for Device 1 (AGP Bridge) disappear and Device 2 (integrated graphics) appear. Propagating the IGE will also enable the graphics clock. FSB PLL Sync (FPLLSYNC)--R/W. 1 0 = After writing a 1, writing a 0 will cause the FSB PLL to synchronize the memory and graphics core clocks to the processor clock. 1 = Writing a 1 will reset the memory and core graphics clock dividers in the FSB FPLL. This will also enable the output of the system memory frequency bits and the Graphics Clock Test Mode register to propagate to the chip and the FPLL. Graphics/Memory Clock Gate (GMCLKGATE)--R/W. 0 = Writing a 0 restarts (enable) the clocks. 1 = Writing a 1 cleanly disables the graphics and memory clocks while still enabling the core clocks. The memory and graphics clocks can then be programmed with new speed information. NOTE: This bit should always be written to before writing to the FPLLSYNC bit. Descriptions
3
0
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Register Description
3.5.18
PAM[0:6]--Programmable Attribute Map Registers (Device 0)
Address Offset: Default Value: Attribute: Size: 90-96h (PAM0-PAM6) 00h R/W, RO 8 bits each register
The GMCH allows programmable memory attributes on 13 legacy memory segments of various sizes in the 640-KB to 1-MB address range. Seven Programmable Attribute Map (PAM) registers are used to support these features. Cacheability of these areas is controlled via the MTRR registers in the processor. Two bits are used to specify memory attributes for each memory segment. These bits apply to host initiator only access to the PAM areas. GMCH will forward to main memory for any AGP, PCI, or HI initiated accesses to the PAM areas. These attributes are: RE Read Enable. When RE = 1, the host read accesses to the corresponding memory segment are claimed by the GMCH and directed to main memory. Conversely, when RE = 0, the host read accesses are directed to PCI_A. Write Enable. When WE = 1, the host write accesses to the corresponding memory segment are claimed by the GMCH and directed to main memory. Conversely, when WE = 0, the host write accesses are directed to PCI_A.
WE
The RE and WE attributes permit a memory segment to be read only, write only, read/write, or disabled. For example, if a memory segment has RE = 1 and WE = 0, the segment is read only. Each PAM register controls two regions, typically 16 KB in size. Each of these regions has a 4-bit field. The four bits that control each region have the same encoding and defined in the following table.
Bits [7, 3] Reserved Bits [6, 2] Reserved Bits [5, 1] WE Bits [4, 0] RE Description Disabled. Main memory is disabled and all accesses are directed to the Hub Interface A. The GMCH does not respond as a PCI target for any read or write access to this area. Read Only. Reads are forwarded to main memory and writes are forwarded to the Hub Interface A for termination. This write protects the corresponding memory segment. The GMCH will respond as an AGP or the Hub Interface target for read accesses but not for any write accesses. Write Only. Writes are forwarded to DRAM and reads are forwarded to the Hub Interface for termination. The GMCH will respond as an AGP or Hub Interface target for write accesses but not for any read accesses. Read/Write. This is the normal operating mode of main memory. Both read and write cycles from the host are claimed by the GMCH and forwarded to main memory. The GMCH will respond as an AGP or the Hub Interface target for both read and write accesses.
X
X
0
0
X
X
0
1
X
X
1
0
X
X
1
1
At the time that a HI or AGP access to the PAM region may occur, the targeted PAM segment must be programmed to be both readable and writable.
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Register Description
As an example, consider BIOS that is implemented on the expansion bus. During the initialization process, BIOS can be shadowed in main memory to increase the system performance. When BIOS is shadowed in main memory, it should be copied to the same address location. To shadow BIOS, the attributes for that address range should be set to write only. The BIOS is shadowed by first doing a read of that address. This read is forwarded to the expansion bus. The host then does a write of the same address that is directed to main memory. After the BIOS is shadowed, the attributes for that memory area are set to read only so that all writes are forwarded to the expansion bus. Figure 8 and Table 7 show the PAM registers and the associated attribute bits. Figure 8. PAM Register Attributes
Offset PAM6 PAM5 PAM4 PAM3 PAM2 PAM1 PAM0 7 R Reserved Reserved Write Enable (R/W) 1=Enable 0=Disable Read Enable (R/W) 1=Enable 0=Disable 6 R 5 WE 4 RE 3 R 2 R 1 WE 0 RE Read Enable (R/W) 1=Enable 0=Disable Write Enable (R/W) 1=Enable 0=Disable Reserved Reserved 96h 95h 94h 93h 92h 91h 90h
Table 7.
PAM Register Attributes
PAM Reg PAM0[3:0] PAM0[7:6] PAM0[5:4] PAM1[1:0] PAM1[7:4] PAM2[1:0] PAM2[7:4] PAM3[1:0] PAM3[7:4] PAM4[1:0] PAM4[7:4] PAM5[1:0] PAM5[7:4] PAM6[1:0] PAM6[7:4] R R R R R R R R R R R R R Attribute Bits Reserved Reserved R R R R R R R R R R R R R WE WE WE WE WE WE WE WE WE WE WE WE WE RE RE RE RE RE RE RE RE RE RE RE RE RE 0F0000h-0FFFFFh 0C0000h-0C3FFFh 0C4000h-0C7FFFh 0C8000h-0CBFFFh 0CC000h-0CFFFFh 0D0000h-0D3FFFh 0D4000h-0D7FFFh 0D8000h-0DBFFFh 0DC000h-0DFFFFh 0E0000h-0E3FFFh 0E4000h-0E7FFFh 0E8000h-0EBFFFh 0EC000h-0EFFFFh BIOS Area ISA Add-on BIOS ISA Add-on BIOS ISA Add-on BIOS ISA Add-on BIOS ISA Add-on BIOS ISA Add-on BIOS ISA Add-on BIOS ISA Add-on BIOS BIOS Extension BIOS Extension BIOS Extension BIOS Extension Memory Segment Comments Offset 90h 90h 90h 91h 91h 92h 92h 93h 93h 94h 94h 95h 95h 96h 96h
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Register Description
For details on overall system address mapping scheme see Chapter 4. DOS Application Area (00000h-9FFFh) The DOS area is 640 KB in size, and it is further divided into two parts. The 512-KB area at 0 to 7FFFFh is always mapped to the main memory controlled by the GMCH, while the 128-KB address range from 080000 to 09FFFFh can be mapped to PCI_A or to main memory. By default this range is mapped to main memory and can be declared as a main memory hole (accesses forwarded to PCI_A) via the GMCH's FDHC configuration register. Video Buffer Area (A0000h-BFFFFh) Attribute bits do not control this 128-KB area. The host-initiated cycles in this region are always forwarded to either PCI_A or AGP unless this range is accessed in SMM mode. Routing of accesses is controlled by the Legacy VGA control mechanism of the virtual PCI-to-PCI bridge device in the GMCH. This area can be programmed as SMM area via the SMRAM register. When used as a SMM space, this range cannot be accessed from the HI or AGP. Expansion Area (C0000h-DFFFFh) This 128 KB area is divided into eight, 16-KB segments, which can be assigned with different attributes via PAM control register as defined by Table 7. Extended System BIOS Area (E0000h-EFFFFh) This 64-KB area is divided into four 16-KB segments that can be assigned with different attributes via the PAM Control register as defined by Table 7. System BIOS Area (F0000h-FFFFFh) This area is a single 64-KB segment that can be assigned with different attributes via PAM control register as defined by Table 7.
3.5.19
FDHC--Fixed Memory(ISA) Hole Control Register (Device 0)
Address Offset: Default Value: Access: Size: 97h 00h R/W, RO 8 bits
This 8-bit register controls a fixed SDRAM hole from 15-16 MB.
Bit Descriptions Hole Enable (HEN)--R/W. This field enables a memory hole in SDRAM space. The SDRAM that lies "behind" this space is not remapped. 0 =Disable. No memory hole. 1 =Enable. Memory hole from 15 MB to 16 MB. 6:0 Reserved.
7
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Register Description
3.5.20
SMRAM--System Management RAM Control Register (Device 0)
Address Offset: Default Value: Access: Size: 9Dh 02h R/W, RO, Lock 8 bits
The SMRAMC register controls how accesses to Compatible and Extended SMRAM spaces are treated. The open, close, and lock bits function only when the G_SMRAME bit is set to 1. Also, the open bit must be reset before the lock bit is set.
Bit 7 6 Reserved. SMM Space Open (D_OPEN)--R/W. When D_OPEN=1 and D_LCK=0, the SMM space SDRAM is made visible, even when SMM decode is not active. This is intended to help BIOS initialize SMM space. Software should ensure that D_OPEN=1 and D_CLS=1 are not set at the same time. SMM Space Closed (D_CLS)--R/W. When D_CLS = 1, SMM space SDRAM is not accessible to data references, even if SMM decode is active. Code references may still access SMM space SDRAM. This will allow SMM software to reference through SMM space to update the display even when SMM is mapped over the VGA range. Software should ensure that D_OPEN=1 and D_CLS=1 are not set at the same time. Note that the D_CLS bit only applies to Compatible SMM space. SMM Space Locked (D_LCK)--R/W. When D_LCK is set to 1, then D_OPEN is reset to 0 and D_LCK, D_OPEN, C_BASE_SEG, H_SMRAM_EN, TSEG_SZ and TSEG_EN become read only. D_LCK can be set to 1 via a normal configuration space write but can only be cleared by a Full Reset. The combination of D_LCK and D_OPEN provide convenience with security. The BIOS can use the D_OPEN function to initialize SMM space and then use D_LCK to "lock down" SMM space in the future so that no application software (or BIOS itself) can violate the integrity of SMM space, even if the program has knowledge of the D_OPEN function. Global SMRAM Enable (G_SMRARE)--R/W/L. If set to 1, Compatible SMRAM functions are enabled, providing 128 KB of SDRAM accessible at the A0000h address while in SMM (ADS# with SMM decode). To enable Extended SMRAM function this bit has to be set to 1. Refer to the section on SMM for more details. Once D_LCK is set, this bit becomes read only. Compatible SMM Space Base Segment (C_BASE_SEG)--RO. This field indicates the location of SMM space. SMM SDRAM is not remapped. It is simply made visible if the conditions are right to access SMM space, otherwise the access is forwarded to HI. Since the GMCH supports only the SMM space between A0000h and BFFFFh, this field is hardwired to 010. Descriptions
5
4
3
2:0
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Register Description
3.5.21
ESMRAMC--Extended System Management RAM Control (Device 0)
Address Offset: Default Value: Access: Size: 9Eh 38h R/W, R/WC, RO, Lock 8 bits
The Extended SMRAM register controls the configuration of Extended SMRAM space. The Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM memory space that is above 1 MB.
Bit Descriptions Enable High SMRAM (H_SMRAME)--R/W/L. This bit controls the SMM memory space location (i.e., above 1 MB or below 1 MB). When G_SMRAME is 1 and H_SMRAME (this bit) is set to 1, the high SMRAM memory space is enabled. SMRAM accesses within the range 0FEDA0000h to 0FEDBFFFFh are remapped to SDRAM addresses within the range 000A0000h to 000BFFFFh. Once D_LCK has been set, this bit becomes read only. Invalid SMRAM Access (E_SMERR)--R/WC. This bit is set when the processor has accessed the defined memory ranges in Extended SMRAM (High Memory and T-segment) while not in SMM space and with the D-OPEN bit = 0. It is software's responsibility to clear this bit. NOTE: Software must write a 1 to this bit to clear it. 5 4 3 SMRAM Cacheable (SM_CACHE)--RO. Hardwired to 1. L1 Cache Enable for SMRAM (SM_L1)--RO. Hardwired to 1. L2 Cache Enable for SMRAM (SM_L2)--RO. Hardwired to 1. TSEG Size (TSEG_SZ)--R/W. This field selects the size of the TSEG memory block, if enabled. Memory from the top of SDRAM space (TOUD +TSEG_SZ) to TOUD is partitioned away so that it may only be accessed by the processor interface and only then when the SMM bit is set in the request packet. Non-SMM accesses to this memory region are sent to HI when the TSEG memory block is enabled. 00 =Reserved 01 =Reserved 10=(TOUD + 512 KB) to TOUD 11 =(TOUD + 1 MB) to TOUD 0 TSEG Enable (T_EN)--R/W/L. This bit enables SMRAM memory for Extended SMRAM space only. When G_SMRAME =1 and TSEG_EN = 1, the TSEG is enabled to appear in the appropriate physical address space. Note that once D_LCK is set, this bit becomes read only.
7
6
2:1
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Register Description
3.5.22
ACAPID--AGP Capability Identifier Register (Device 0)
Address Offset: Default Value: Access: Size: A0h-A3h 00300002h RO 32 bits
This register provides standard identifier for AGP capability.
Bit 31:24 23:20 Reserved. Major AGP Revision Number (MAJREV)--RO. These bits provide a major revision number of AGP specification to which this version of GMCH conforms. This field is hardwired to value of 0011b (i.e., implying Rev 3.x). Minor AGP Revision Number (MINREV)--RO. These bits provide a minor revision number of AGP specification to which this version of GMCH conforms. This number is hardwired to value of 0000 which implies that the revision is x.0. Together with major revision number this field identifies the GMCH as an AGP Rev 3.0 compliant device. Next Capability Pointer (NCAPTR)--RO. AGP capability is the first and the last capability described via the capability pointer mechanism and therefore these bits are hardwired to 0 to indicate the end of the capability linked list. AGP Capability ID (CAPID)--RO. This field identifies the linked list item as containing AGP registers. This field has a value of 0000_0010b assigned by the PCI SIG. Descriptions
19:16
15:8 7:0
3.5.23
AGPSTAT--AGP Status Register (Device 0)
Address Offset: Default Value: Access: Size: A4-A7h 1F004217h in AGP 2.0 mode 1F004A13h in AGP 3.0 mode RO 32 bits
This register reports AGP device capability/status.
Bit 31:24 23:16 Descriptions Request Queue (RQ)--RO. Hardwired to 1Fh to indicate that a maximum of 32 outstanding AGP command requests can be handled by the GMCH. This field contains the maximum number of AGP command requests the GMCH is configured to manage. Reserved. ARQSZ--RO. This field is LOG2 of the optimum asynchronous request size in bytes minus 4 to be used with the target. The master should attempt to issue a group of sequential back-to-back asynchronous requests that total to this size and for which the group is naturally aligned. Optimum_request_size = 2 ^ (ARQSZ+4). Hardwired to 010 to indicate 64 B 12:10 9 8:6 5 CAL_Cycle--RO. This field specifies the required period for GMCH initiated bus cycle for calibrating I/O buffers. Hardwired to 010, indicating 64 ms. Side Band Addressing Support (SBA)--RO. Hardwired to 1, indicating that the GMCH supports side band addressing. Reserved. Greater Than Four Gigabyte Support (GT4GIG)--RO. Hardwired to 0, indicating that the GMCH does not support addresses greater than 4 GB.
15:13
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Intel(R) 82865G/82865GV GMCH Datasheet
Register Description
Bit 4
Descriptions Fast Write Support (FW)--RO. Hardwired to 1, indicating that the GMCH supports Fast Writes from the processor to the AGP master. AGP 3.0 mode (AGP 30_MOD--RO. This bit is set by the hardware on the assertion of PWROK based on the AGP 3.0 detection via the Vref comparator on the GVREF pin. In AGP 2.0 mode, GVREF is driven to 0.75 V, while in AGP 3.0 mode, GVREF is driven to 0.35 V. Note that the output of the Vref comparator is used "live" prior to the assertion of PWROK and used to select the appropriate pull-up, pull-down or termination on the I/O buffer depending on the mode selected. 0 = AGP 2.0 (1.5 V signaling) mode. 1 = AGP 3.0 signaling mode. Data Rate Support (RATE)--RO. After reset, the GMCH reports its data transfer rate capability. AGP 2.0 Mode * Bit 0 identifies if AGP device supports 1X data transfer mode, * Bit 1 identifies if AGP device supports 2X data transfer mode, (unsupported) * Bit 2 identifies if AGP device supports 4X data transfer. AGP 3.0 Mode
3
2:0
* Bit 0 identifies if AGP device supports 4X data transfer mode, * Bit 1 identifies if AGP device supports 8X data transfer mode, * Bit 2 is reserved. NOTES: 1. In AGP 3.0 mode (AGP_MODE=1) these bits are 011 indicating that both 4X and 8X modes are supported. 2. In AGP 2.0 mode these bits are 111 indicating that 4X, 2X, and 1X modes are supported; however, in the 82865G GMCH 2X is not supported.
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Register Description
3.5.24
AGPCMD--AGP Command Register (Device 0)
Address Offset: Default Value: Access: Size: A8-ABh 00000000h in AGP 2.0 mode 00000A00h in AGP 3.0 mode RO, R/W 32 bits
This register provides control of the AGP operational parameters.
Bit 31:13 Reserved. PCAL_Cycle--R/W. This filed is programmed with the period for GMCH-initiated bus cycle for calibrating I/O buffers for both master and target. This value is updated with the smaller of the value in CAL_CYCLE from Master's and Target's AGPSTAT.CAL_CYCLE. PCAL_CYCLE is set to 111 by software only if both the Target and Master have AGPSTAT.CAL_CYCLE = 111. 12:10 000 = 4 ms 001 = 16 ms 010 = 64 ms (Default). 011 = 256 ms 100-110 = Reserved 111 = Calibration Cycle Not Needed Side Band AddressingEnable (SBAEN)--R/W. This bit is ignored in AGP 3.0 mode to allow legacy 2.0 software to work. (When AGP 3.0 is detected, sideband addressing mechanism is automatically enabled by the hardware.) 0 = Disable. 1 = Enable. Side band addressing mechanism is enabled. AGP Enable (AGPEN)--R/W. 8 0 = Disable. GMCH ignores all AGP operations, including the sync cycle. Any AGP operations received while this bit is set to 1 will be serviced, even if this bit is reset to 0. If this bit transitions from 1 to 0 on a clock edge in the middle of an SBA command being delivered in 1X mode, the command will be issued. 1 = Enable. GMCH responds to AGP operations delivered via PIPE#, or to operations delivered via SBA if the AGP Side Band Enable bit is also set to 1. Reserved. Greater Than Four Gigabyte Enable (GT4GIGE)--RO. Hardwired to 0 indicating that the GMCH, as an AGP target, does not support addressing greater than 4 GB. Fast Write Enable (FWEN)--R/W. 4 0 = Disable. When this bit is cleared, or when the data rate bits are set to 1X mode, the memory write transactions from the GMCH to the AGP master use standard PCI protocol. 1 = Enable. The GMCH uses the Fast Write protocol for memory write transactions from the GMCH to the AGP master. Fast Writes will occur at the data transfer rate selected by the data rate bits (2:0) in this register. Reserved. Data Rate Enable (DRATE)--R/W. The setting of these bits determines the AGP data transfer rate. One (and only one) bit in this field must be set to indicate the desired data transfer rate. The same bit must be set on both master and target. AGP 2.0 2:0 001= 1X Transfer Mode (for AGP 2.0 signaling) 010= 2X Transfer Mode (NOT SUPPORTED) 100= 4X Transfer Mode (for AGP 2.0 signaling) AGP 3.0 001= 4X transfer mode (for AGP 3.0 signaling) 010= 8X Transfer mode (for AGP 3.0 signaling) 100= Reserved Descriptions
9
7:6 5
3
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Intel(R) 82865G/82865GV GMCH Datasheet
Register Description
3.5.25
AGPCTRL--AGP Control Register (Device 0)
Address Offset: Default Value: Access: Size: B0-B3h 00000000h RO, R/W 32 bits
This register provides for additional control of the AGP interface.
Bit 31:8 Reserved. GTLB Enable (GTLBEN)-- R/W. 0 = Disable (default). The GTLB is flushed by clearing the valid bits associated with each entry. In this mode of operation: -- All accesses that require translation bypass the GTLB -- All requests that are positively decoded to the graphics aperture force the GMCH to access the translation table in main memory before completing the request -- Valid translation table entry fetches will not be cached in the GTLB -- Invalid translation table entry fetches will still be cached in the GTLB (ejecting the least recently used entry). 1 = Enable. Normal operations of the Graphics Translation Lookaside Buffer are enabled. NOTE: This bit can be changed dynamically (i.e., while an access to GTLB occurs); however, the completion of the configuration write that asserts or deasserts this bit will be delayed pending a complete flush of all dirty entries from the write buffer. This delay will be incurred because this bit is used as a mechanism to signal the chipset that the graphics aperture translation table is about to be modified or has completed modifications. In the first case, all dirty entries need to be flushed before the translation table is changed. In the second case, all dirty entries need to be flushed because one of them is likely to be a translation table entry which must be made visible to the GTLB by flushing it to memory. 6:1 Reserved. 4X Override (OVER4X)--R/W. This back-door register bit allows the BIOS to force 1X mode for AGP 2.0 and 4X mode for AGP 3.0. Note that this bit must be set by the BIOS before AGP configuration. 0 = No override 1 = The RATE[2:0] bit in the AGPSTS register will be read as a 001. Descriptions
7
0
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Register Description
3.5.26
APSIZE--Aperture Size Register (Device 0)
Address Offset: Default Value: Access: Size: B4h 00h RO, R/W 8 bits
This register determines the effective size of the graphics aperture used for a particular GMCH configuration. This register can be updated by the GMCH-specific BIOS configuration sequence before the PCI standard bus enumeration sequence takes place. If the register is not updated, then a default value will select an aperture of maximum size (i.e., 256 MB). The size of the table that will correspond to a 256-MB aperture is not practical for most applications; therefore, these bits must be programmed to a smaller practical value that will force adequate address range to be requested via APBASE register from the PCI configuration software.
Bit 7:6 Reserved. Graphics Aperture Size (APSIZE)--R/W. Each bit in APSIZE[5:0] operates on similarly ordered bits in APBASE[27:22] of the Aperture Base configuration register. When a particular bit of this field is 0, it forces the similarly ordered bit in APBASE[27:22] to behave as hardwired to 0. When a particular bit of this field is set to 1, it allows the corresponding bit of the APBASE[27:22] to be read/write accessible. The default value (APSIZE[5:0]=000000b) forces the default APBASE[27:22] to read as 000000b (i.e., all bits respond as hardwired to 0). This provides the maximum aperture size of 256 MB. As another example, programming APSIZE[5:0] to 111000b hardwires APBASE[24:22] to 000b and enables APBASE[27:25] to be read/write programmable. 5:0 000000 = 256-MB aperture size 100000 = 128-MB aperture size 110000 = 64-MB aperture size 111000 = 32-MB aperture size 111100 = 16-MB aperture size 111110 = 8-MB aperture size 111111 = 4-MB aperture size Descriptions
3.5.27
ATTBASE--Aperture Translation Table Register (Device 0)
Address Offset: Default Value: Access: Size: B8-BBh 00000000h RO, R/W 32 bits
This register provides the starting address of the Graphics Aperture Translation Table Base located in the main memory. This value is used by the GMCH's graphics aperture address translation logic (including the GTLB logic) to obtain the appropriate address translation entry required during the translation of the aperture address into a corresponding physical main memory address. The ATTBASE register may be dynamically changed.
Bit 31:12 11:0 Descriptions Aperture Translation Table Base (TTABLE)--R/W. This field contains a pointer to the base of the translation table used to map memory space addresses in the aperture range to addresses in main memory. Note that it should be modified only when the GTLB has been disabled. Reserved.
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Intel(R) 82865G/82865GV GMCH Datasheet
Register Description
3.5.28
AMTT--AGP MTT Control Register (Device 0)
Address Offset: Default Value: Access: Size: BCh 10h RO, R/W 8 bits
AMTT is an 8-bit register that controls the amount of time that the GMCH's arbiter allows AGP/ PCI master to perform multiple back-to-back transactions. The GMCH's AMTT mechanism is used to optimize the performance of the AGP master (using PCI semantics) that performs multiple backto-back transactions to fragmented memory ranges (and as a consequence it can not use long burst transfers). The AMTT mechanism applies to the Processor-AGP/PCI transactions as well and it assures the processor of a fair share of the AGP/PCI interface bandwidth. The number of clocks programmed in the AMTT represents the guaranteed time slice (measured in 66 MHz clocks) allotted to the current agent (either AGP/PCI master or Host bridge) after which the AGP arbiter will grant the bus to another agent. The default value of AMTT is 00h and disables this function. The AMTT value can be programmed with 8-clock granularity. For example, if the AMTT is programmed to 18h, then the selected value corresponds to the time period of 24 AGP (66 MHz) clocks. Set by BIOS.
Bit Descriptions Multi-Transaction Timer Count Value (MTTC)--R/W. The number programmed into these bits represents the time slice (measured in eight, 66 MHz clock granularity) allotted to the current agent (either AGP/PCI master or Host bridge) after which the AGP arbiter will grant the bus to another agent. Reserved.
7:3 2:0
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Register Description
3.5.29
LPTT--AGP Low Priority Transaction Timer Register (Device 0)
Address Offset: Default Value: Access: Size: BDh 10h RO, R/W 8 bits
LPTT is an 8-bit register similar in function to AMTT. This register is used to control the minimum tenure on the AGP for low priority data transaction (both reads and writes) issued using PIPE# or SB mechanisms. The number of clocks programmed in the LPTT represents the guaranteed time slice (measured in 66 MHz clocks) allotted to the current low priority AGP transaction data transfer state. This does not necessarily apply to a single transaction but it can span over multiple low-priority transactions of the same type. After this time expires, the AGP arbiter may grant the bus to another agent if there is a pending request. The LPTT does not apply in the case of high-priority request where ownership is transferred directly to high-priority requesting queue. The default value of LPTT is 00h and disables this function. The LPTT value can be programmed with 8-clock granularity. For example, if the LPTT is programmed to 10h, the selected value corresponds to the time period of 16 AGP (66 MHz) clocks.
Bit 7:3 2:0 Descriptions Low Priority Transaction Timer Count Value (LPTTC)--R/W. The number of clocks programmed in these bits represents the time slice (measured in eight 66 MHz clock granularity) allotted to the current low priority AGP transaction data transfer state. Reserved.
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Intel(R) 82865G/82865GV GMCH Datasheet
Register Description
3.5.30
TOUD--Top of Used DRAM Register (Device 0)
Address Offset: Default Value: Access: Size:
Bit
C4-C5h 0400h RO, R/W 16 bits
Descriptions
Top of Usable DRAM (TOUD)--R/W. This register contains bits 31:19 of the maximum system memory address that is usable by the operating system. Address bits 31:19 imply a memory granularity of 512 KB. Configuration software should set this value to either the maximum amount of usable memory (minus TSEG, graphics stolen memory, and CSA stolen memory) in the system or to the minimum address allocated for PCI memory or the graphics aperture (minus TSEG, graphics stolen memory), whichever is smaller. Address bits 18:0 are assumed to be 0000h for the purposes of address comparison. This register must be set to at least 0400h for a minimum of 64 MB of system memory. To calculate the value of TOUD, configuration software should set this value to the smaller of the following 2 cases: * The maximum amount of usable memory in the system minus optional TSEG, optional graphics stolen memory. * The address allocated for PCI memory or the graphics aperture minus optional TSEG, optional graphics stolen memory. Programming Example: * DRB7 is set to 4 GB. 15:3 * TSEG is enabled and TSEG size is set to 1 MB. * Internal Graphics is enabled and Graphics Mode Select is set to 32 MB. * BIOS knows the OS requires 1 GB of PCI space. * BIOS also knows the range from FEC0_0000h to FFFF_FFFFh is not usable by the system. This 20-MB range at the very top of addressable memory space is lost to APIC. According to the above equation, TOUD is originally calculated to: * 4 GB (DRB7) - 1 MB (TSEG) - 32 MB (graphics) = FDF0_0000h The system memory requirements are: * 4 GB (max addressable space) - 1 GB (PCI space) - 33 MB (TSEG, graphics) - 20 MB (lost memory) = BCB0_0000h Since BCB0_0000h (PCI and other system memory requirements) is less than FDF0_0000h, TOUD should be programmed to BCB0_0000h. NOTE: Even if the OS does not need any PCI space, TOUD should never be programmed above FEC0_0000h. If TOUD is programmed above this, address ranges that are reserved will become accessible to applications. 2:0 Reserved.
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Register Description
3.5.31
GMCHCFG--GMCH Configuration Register (Device 0)
Address Offset: Default Value: Access: Size:
Bit
C6-C7h 0000h R/W, RO 16 bits
Descriptions
15:13
Number of Stop Grant Cycles (NSG)--R/W. This field contains the number of Stop Grant transactions expected on the FSB bus before a Stop Grant Acknowledge packet is sent to the ICH5. This field is programmed by the BIOS after it has enumerated the processors and before it has enabled Stop Clock generation in the ICH5. Once this field has been set, it should not be modified. Note that each enabled thread within each processor will generate Stop Grant Acknowledge transactions. 000 = HI Stop Grant sent after 1 FSB Stop Grant 001 = HI Stop Grant sent after 2 FSB Stop Grants 010-111= Reserved
12
Reserved System Memory Frequency Select (SMFREQ)--R/W. Default = 00. The DDR memory frequency is determined by the following table and partly determined by the FSB frequency. FSBFREQ[1:0] =00 FSBFREQ[1:0] =01 FSBFREQ[1:0] =01 SMFREQ[11:10]=01 SMFREQ[11:10]=00 SMFREQ[11:10]=01 SMFREQ[11:10]=01 SMFREQ[11:10]=10 System Memory DDR set to 266 MHz System Memory DDR set to 266 MHz System Memory DDR set to 333 MHz System Memory DDR set to 333 (320) MHz System Memory DDR set to 400 MHz
11:10
FSBFREQ[1:0] =10 FSBFREQ[1:0] =10 All others are Reserved
Note that Memory I/O Clock always runs at 2x the frequency of the memory clock. When writing a new value to this register, software must perform a clock synchronization sequence to apply the new timings. The new value does not get applied until this is completed. 9:6 Reserved MDA Present (MDAP)--R/W. This bit works with the VGA Enable bits in the BCTRL1 register of Device 1 to control the routing of processor-initiated transactions targeting MDA compatible I/O and memory address ranges. This bit should not be set if Device 1's VGA Enable bit is not set. If Device 1's VGA enable bit is not set, then accesses to I/O address range x3BCh-x3BFh are forwarded to HI. If the VGA enable bit is not set, then accesses to I/O address range x3BCh- x3BFh are treated just like any other I/O accesses. That is, the cycles are forwarded to AGP if the address is within the corresponding IOBASE and IOLIMIT and ISA enable bit is not set; otherwise, they are forwarded to HI. MDA resources are defined as the following: Memory: I/O: 5 0B0000h - 0B7FFFh 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh, (including ISA address aliases, A[15:10] are not used in decode)
Any I/O reference that includes the I/O locations listed above, or their aliases, will be forwarded to the hub interface, even if the reference includes I/O locations not listed above. The following table shows the behavior for all combinations of MDA and VGA: VGA 0 0 1 1 MDA 0 1 0 1 Behavior All references to MDA and VGA go to HI. Illegal combination (DO NOT USE). All references to VGA go to Device 1. MDA-only references (I/O address 3BFh and aliases) will go to HI. VGA references go to AGP/PCI; MDA references go to HI.
4
Reserved
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Register Description
Bit
Descriptions AGP Mode (AGP/DVO#)--RO. This bit reflects the GPAR/ADD_DETECT# strap value. This strap bit determines the function of the AGP I/O pins. Note that the strap value is sampled on the assertion of PWROK. 0 = 2xDVO 1 = AGP When the strap is sampled low, this bit will be a 0 and DVO mode will be selected. When the strap is sampled high, this bit will be a 1 and AGP mode will be selected. In addition, this bit is forced to 1 if the AGP 3.0 detect bit (AGPSTAT.3) is 1. This is shown in the following table: AGP 30_MOD bit 0 0 1 ADD_DETECT Strap 0 1 x Resulting AGP/DVO# 0 1 1
3
NOTE: When this bit is set to 0 (DVO Mode), AGP is disabled (configuration cycles fall-through to HI) and the Next Pointer field in CAPREG in Device 0 will be hardwired to all 0s. FSB IOQ Depth (IOQD)--RO. This bit reflects the HA7# strap value. It indicates the depth of the FSB IOQ. When the strap is sampled low, this bit will be a 0 and the FSB IOQ depth is set to 1. When the strap is sampled high, this bit will be a 1 and the FSB IOQ depth is set to the maximum (12 on the bus, 12 on the GMCH). 0 = 1 deep 1 = 12 on the bus, 12 on the GMCH FSB Frequency Select (FSBFREQ)--RO. The default value of this bit is set by the strap assigned to the BSEL[1:0] pins and is latched at the rising edge of PWROK. 1:0 00 = Core Frequency is 100 MHz and the FSB frequency is 400 MHz 01 = Core Frequency is 133 MHz and the FSB frequency is 533 MHz 10 = Core Frequency is 200 MHz and the FSB frequency is 800 MHz 11 = Reserved
2
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Register Description
3.5.32
ERRSTS--Error Status Register (Device 0)
Address Offset: Default Value: Access: Size: C8-C9h 0000h R/WC 16 bits
This register is used to report various error conditions via the SERR HI messaging mechanism. A SERR HI message is generated on a 0-to-1 transition of any of these flags (if enabled by the ERRCMD and PCICMD registers). These bits are set regardless of whether or not the SERR is enabled and generated. Note: Software must write a 1 to clear bits that are set.
Bit 15:10 9 Reserved Non-DRAM Lock Error (NDLOCK)--R/WC. 0 = No Lock operation detected. 1 = GMCH has detected a lock operation to memory space that did not map into SDRAM. Software Generated SMI Flag--R/WC. 8 7:6 5 0 = Source of an SMI was not the Device 2 Software SMI Trigger. 1 = Source of an SMI was the Device 2 Software SMI Trigger. Reserved GMCH Detects Unimplemented HI Special Cycle (HIAUSC)--R/WC. 0 = No unimplemented Special Cycle on HI detected. 1 = GMCH detects an Unimplemented Special Cycle on HI. AGP Access Outside of Graphics Aperture Flag (OOGF)--R/WC. 4 0 = No AGP access outside of the graphics aperture range. 1 = AGP access occurred to an address that is outside of the graphics aperture range. Invalid AGP Access Flag (IAAF)--R/WC. 3 0 = No invalid AGP Access Flag. 1 = AGP access was attempted outside of the graphics aperture and either to the 640 KB - 1 MB range or above the top of memory. Invalid Graphics Aperture Translation Table Entry (ITTEF)--R/WC. 2 0 = No Invalid Graphics Aperture Translation Table Entry. 1 = Invalid translation table entry was returned in response to an AGP access to the graphics aperture. GMCH Detects Unsupported AGP Command--R/WC. 1 0 0 = No unsupported AGP Command received. 1 = Bogus or unsupported command is received by the AGP target in the GMCH. Reserved Descriptions
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Register Description
3.5.33
ERRCMD--Error Command Register (Device 0)
Address Offset: Default Value: Access: Size: CA-CBh 0000h RO, R/W 16 bits
This register controls the GMCH responses to various system errors. Since the GMCH does not have a SERR# signal, SERR messages are passed from the GMCH to the ICH5 over HI. When a bit in this register is set, a SERR message will be generated on HI when the corresponding flag is set in the ERRSTS register. The actual generation of the SERR message is globally enabled for Device 0 via the PCI Command register.
Bit 15:10 Reserved SERR on Non-DRAM Lock (LCKERR)--R/W. 9 0 =Disable 1 =Enable. The GMCH generates a HI SERR special cycle when a processor lock cycle is detected that does not hit system memory. Reserved SERR on Target Abort on HI Exception (TAHLA)--R/W. 6 0 =Reporting of this condition is disabled. 1 =GMCH generates a SERR special cycle over HI when an GMCH originated HI cycle is completed with a target abort completion packet or special cycle. SERR on Detecting HI Unimplemented Special Cycle (HIAUSCERR)--R/W. 5 0 =GMCH does not generate a SERR message for this event. SERR messaging for Device 0 is globally enabled in the PCICMD register. 1 =GMCH generates a SERR message over HI when an Unimplemented Special Cycle is received on the HI. SERR on AGP Access Outside of Graphics Aperture (OOGF)--R/W. 4 0 =Reporting of this condition is disabled. 1 =Enable. GMCH generates a SERR special cycle over HI when an AGP access occurs to an address outside of the graphics aperture. SERR on Invalid AGP Access (IAAF)--R/W. 0 =Invalid AGP Access condition is not reported. 3 1 =GMCH generates a SERR special cycle over HI when an AGP access occurs to an address outside of the graphics aperture and either to the 640 KB - 1 MB range or above the top of memory. SERR on Invalid Translation Table Entry (ITTEF)--R/W. 2 0 =Reporting of this condition is disabled. 1 =GMCH generates a SERR special cycle over HI when an invalid translation table entry was returned in response to an AGP access to the graphics aperture. SERR on GMCH Detects Unsupported AGP Command--R/W. 1 0 0 =GMCH Detects Unsupported AGP command will not generate a SERR. 1 =GMCH generates a SERR when an unsupported AGP command is detected. Reserved Descriptions
8:7
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Register Description
3.5.34
SKPD--Scratchpad Data Register (Device 0)
Address Offset: Default Value: Access: Size:
Bit 15:0
DE-DFh 0000h R/W 16 bits
Descriptions
Scratchpad (SCRTCH)--R/W. These bits are R/W storage bits that have no effect on the GMCH functionality.
3.5.35
CAPREG--Capability Identification Register (Device 0)
Address Offset: Default: Access: Size E4h-E9h 00000106A009h RO 48 bits
The Capability Identification register uniquely identifies chipset capabilities as defined in the table below.
Bit 47:28 27:24 23:16 15:8 7:0 Reserved. CAPREG Version--RO. This field has the value 0001b to identify the first revision of the CAPREG definition. Cap_length--RO. This field has the value 06h indicating the structure length. Next_Pointer--RO. This field has the value A0h pointing to the next capabilities register, AGP Capability Identifier register (ACAPID). If AGP is disabled, this field has the value 00h signifying the end of the capabilities linked list. CAP_ID--RO. This field has the value 09h to identify the CAP_ID assigned by the PCI SIG for Vendor Dependent CAP_PTR. Descriptions
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Register Description
3.6
PCI-to-AGP Bridge Configuration Register (Device 1)
This section contains the PCI-to-AGP bridge PCI configuration registers listed in order of ascending offset address. The register address map is shown in Table 8.
Table 8.
PCI-to-AGP Bridge PCI Configuration Register Address Map (Device 1)
Address Offset 00-01h 02-03h 04-05h 06-07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0F-17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1E-1Fh 20-21h 22-23h 24-25h 26-27h 28-3Dh 3Eh 3Fh 40h 41-FFh Register Symbol VID1 DID1 PCICMD1 PCISTS1 RID1 -- SUBC1 BCC1 -- MLT1 HDR1 -- PBUSN1 SBUSN1 SUBUSN1 SMLT1 IOBASE1 IOLIMIT1 SSTS1 MBASE1 MLIMIT1 PMBASE1 PMLIMIT1 -- BCTRL1 -- ERRCMD1 -- Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Reserved Sub-Class Code Base Class Code Reserved Master Latency Timer Header Type Reserved Primary Bus Number Secondary Bus Number Subordinate Bus Number Secondary Bus Master Latency Timer I/O Base Address I/O Limit Address Secondary Status Memory Base Address Memory Limit Address Prefetchable Memory Base Address Prefetchable Memory Limit Address Reserved Bridge Control Reserved Error Command Reserved Default Value 8086h 2571h 0000h 00A0h See register description -- 04h 06h -- 00h 01h -- 00h 00h 00h 00h F0h 00h 02A0h FFF0h 0000h FFF0h 0000h -- 00h -- 00h -- Access RO RO RO, R/W RO, R/WC RO -- RO RO -- RO, R/W RO -- RO R/W R/W RO, R/W RO, R/W RO, R/W RO, R/WC RO, R/W RO, R/W RO, R/W RO, R/W -- RO, R/W -- RO, R/W --
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Register Description
3.6.1
VID1--Vendor Identification Register (Device 1)
Address Offset: Default Value: Access: Size: 00-01h 8086h RO 16 bits
The VID register contains the vendor identification number. This 16-bit register, combined with the Device Identification register, uniquely identify any PCI device.
Bit 15:0 Descriptions Vendor Identification Device 1 (VID1)--RO. This register field contains the PCI standard identification for Intel, 8086h.
3.6.2
DID1--Device Identification Register (Device 1)
Address Offset: Default Value: Access: Size: 02-03h 2571h RO 16 bits
This 16-bit register, combined with the Vendor Identification register, uniquely identifies any PCI device.
Bit 15:0 Descriptions Device Identification Number (DID)--RO. A 16-bit value assigned to the GMCH device 1.
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Register Description
3.6.3
PCICMD1--PCI Command Register (Device 1)
Address Offset: Default Value: Access: Size:
Bit 15:10 9 Reserved. Fast Back-to-Back Enable (FB2B)--RO. Hardwired to 0. SERR Message Enable (SERRE)--R/W. This bit is a global enable bit for Device 1 SERR messaging. The GMCH communicates the SERR# condition by sending a SERR message to the ICH5. 8 0 = Disable. SERR message is not generated by the GMCH for Device 1. 1 = Enable. GMCH is enabled to generate SERR messages over HI for specific Device 1 error conditions that are individually enabled in the BCTRL1 register. The error status is reported in the PCISTS1 register. Address/Data Stepping (ADSTEP)--RO. Hardwired to 0. Parity Error Enable (PERRE)--RO. Hardwired to 0. Parity checking is not supported on the primary side of this device. Reserved. Memory Write and Invalidate Enable (MWIE)--RO. Hardwired to 0. Special Cycle Enable (SCE)--RO. Hardwired to 0. Bus Master Enable (BME)--R/W. 2 0 = Disable. AGP Master initiated Frame# cycles will be ignored by the GMCH. The result is a master abort. Ignoring incoming cycles on the secondary side of the PCI-to-PCI bridge effectively disabled the bus master on the primary side. (default) 1 = Enable. AGP master initiated Frame# cycles will be accepted by the GMCH if they hit a valid address decode range. This bit has no affect on AGP Master originated SBA or PIPE# cycles. Memory Access Enable (MAE)--R/W. 1 0 = Disable. All of Device 1's memory space is disabled. 1 = Enable. Enables the memory and pre-fetchable memory address ranges defined in the MBASE1, MLIMIT1, PMBASE1, and PMLIMIT1 registers. IO Access Enable (IOAE)--R/W. 0 0 = Disable. All of Device 1's I/O space is disabled. 1 = Enable. This bit must be set to1 to enable the I/O address range defined in the IOBASE1, and IOLIMIT1 registers.
04-05h 0000h RO, R/W 16 bits
Descriptions
7 6 5 4 3
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Register Description
3.6.4
PCISTS1--PCI Status Register (Device 1)
Address Offset: Default Value: Access: Size: 06-07h 00A0h RO, R/WC 16 bits
PCISTS1 is a 16-bit status register that reports the occurrence of error conditions associated with primary side of the virtual PCI-to-PCI bridge in the GMCH.
Bit 15 Descriptions Detected Parity Error (DPE)--RO. Hardwired to 0. Parity is not supported on the primary side of this device. Signaled System Error (SSE)--R/WC. 0 =Software clears this bit by writing a 1 to it. 14 1 =GMCH Device 1 generated a SERR message over HI for any enabled Device 1 error condition. Device 1 error conditions are enabled in the ERRCMD, PCICMD1 and BCTRL1 registers. Device 1 error flags are read/reset from the ERRSTS and SSTS1 register. Received Master Abort Status (RMAS)--RO. Hardwired to 0. The concept of a master abort does not exist on primary side of this device. Received Target Abort Status (RTAS)--RO. Hardwired to 0. The concept of a target abort does not exist on primary side of this device. Signaled Target Abort Status (STAS)--RO. Hardwired to 0. The concept of a target abort does not exist on primary side of this device. DEVSEL# Timing (DEVT)--RO. The GMCH does not support subtractive decoding devices on bus 0. Therefore, this field is hardwired to 00 indicating that Device 1 uses the fastest possible decode. Data Parity Detected (DPD)--RO. Hardwired to 0. Parity is not supported on the primary side of this device. Fast Back-to-Back (FB2B)--RO. Hardwired to 1. The AGP/PCI_B interface always supports fast back-to-back writes. Reserved. 66/60 MHz capability (CAP66)--RO. Hardwired to 1. The AGP/PCI bus is 66 MHz capable. Reserved.
13 12 11 10:9 8 7 6 5 4:0
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Register Description
3.6.5
RID1--Revision Identification Register (Device 1)
Address Offset: Default Value: Access: Size: 08h See table below RO 8 bits
This register contains the revision number of the GMCH Device 1.
Bit 7:0 Descriptions Revision Identification Number (RID)--RO. This is an 8-bit value that indicates the revision identification number for the GMCH Device 1. It is always the same as the value in RID. 02h = A-2 Stepping
3.6.6
SUBC1--Sub-Class Code Register (Device 1)
Address Offset: Default Value: Access: Size: 0Ah 04h RO 8 bits
This register contains the Sub-Class Code for the GMCH Device 1.
Bit 7:0 Descriptions Sub-Class Code (SUBC)--RO. This is an 8-bit value that indicates the category of bridge for the Device 1 of the GMCH. 04h = PCI-to-PCI bridge.
3.6.7
BCC1--Base Class Code Register (Device 1)
Address Offset: Default Value: Access: Size: 0Bh 06h RO 8 bits
This register contains the Base Class Code of the GMCH Device 1.
Bit 7:0 Descriptions Base Class Code (BASEC)--RO. This is an 8-bit value that indicates the Base Class Code for the GMCH Device 1. 06h = Bridge device.
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Register Description
3.6.8
MLT1--Master Latency Timer Register (Device 1)
Address Offset: Default Value: Access: Size: 0Dh 00h RO, R/W 8 bits
This functionality is not applicable. It is described here since these bits should be implemented as read/write to prevent standard PCI-to-PCI bridge configuration software from getting "confused."
Bit 7:3 2:0 Descriptions Scratchpad MLT (NA7.3)--R/W. These bits return the value with which they are written; however, they have no internal function and are implemented as a scratchpad to avoid confusing software. Reserved.
3.6.9
HDR1--Header Type Register (Device 1)
Address Offset: Default Value: Access: Size: 0Eh 01h RO 8 bits
This register identifies the header layout of the configuration space. No physical register exists at this location.
Bit 7:0 Descriptions Header Type Register (HDR)--RO. This read only field always returns 01 to indicate that GMCH Device 1 is a single function device with bridge header layout.
3.6.10
PBUSN1--Primary Bus Number Register (Device 1)
Address Offset: Default Value: Access: Size: 18h 00h RO 8 bits
This register identifies that virtual PCI-to-PCI bridge is connected to bus 0.
Bit 7:0 Descriptions Primary Bus Number (PBUSN)--RO. Configuration software typically programs this field with the number of the bus on the primary side of the bridge. Since Device 1 is an internal device and its primary bus is always 0, these bits are read only and are hardwired to 0.
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Register Description
3.6.11
SBUSN1--Secondary Bus Number Register (Device 1)
Address Offset: Default Value: Access: Size: 19h 00h R/W 8 bits
This register identifies the bus number assigned to the second bus side of the virtual PCI-to-PCI bridge (i.e., to PCI_B/AGP). This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI_B/AGP.
Bit 7:0 Descriptions Secondary Bus Number (SBUSN)--RO. This field is programmed by configuration software with the bus number assigned to PCI_B.
3.6.12
SUBUSN1--Subordinate Bus Number Register (Device 1)
Address Offset: Default Value: Access: Size: 1Ah 00h R/W 8 bits
This register identifies the subordinate bus (if any) that resides at the level below PCI_B/AGP. This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI_B/AGP.
Bit Descriptions Subordinate Bus Number (BUSN)--R/W. This register is programmed by configuration software with the number of the highest subordinate bus that lies behind the Device 1 bridge. When only a single PCI device resides on the AGP/PCI_B segment, this register will contain the same value as the SBUSN1 register.
7:0
3.6.13
SMLT1--Secondary Bus Master Latency Timer Register (Device 1)
Address Offset: Default Value: Access: Size: 1Bh 00h RO, R/W 8 bits
This register control the bus tenure of the GMCH on AGP/PCI the same way Device 0 MLT controls the access to the PCI_A bus.
Bit 7:3 2:0 Descriptions Secondary MLT Counter Value (MLT)--R/W. Programmable, default = 0 (SMLT disabled) Reserved.
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Register Description
3.6.14
IOBASE1--I/O Base Address Register (Device 1)
Address Offset: Default Value: Access: Size: 1Ch F0h RO, R/W 8 bits
This register controls the processor-to-PCI_B/AGP I/O access routing based on the following formula:
IO_BASE address IO_LIMIT
Only the upper 4 bits are programmable. For the purpose of address decode, address bits A[11:0] are treated as 0. Thus, the bottom of the defined I/O address range will be aligned to a 4-KB boundary.
Bit 7:4 3:0 Descriptions I/O Address Base (IOBASE)--R/W. This field corresponds to A[15:12] of the I/O addresses passed by bridge 1 to AGP/PCI_B. Reserved.
3.6.15
IOLIMIT1--I/O Limit Address Register (Device 1)
Address Offset: Default Value: Access: Size: 1Dh 00h RO, R/W 8 bits
This register controls the processor-to-PCI_B/AGP I/O access routing based on the following formula:
IO_BASE address IO_LIMIT
Only the upper 4 bits are programmable. For the purpose of address decode, address bits A[11:0] are assumed to be FFFh. Thus, the top of the defined I/O address range will be at the top of a 4-KB aligned address block.
Bit 7:4 3:0 Descriptions I/O Address Limit (IOLIMIT)--R/W. This field corresponds to A[15:12] of the I/O address limit of Device 1. Devices between this upper limit and IOBASE1 will be passed to AGP/PCI_B. Reserved.
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Register Description
3.6.16
SSTS1--Secondary Status Register (Device 1)
Address Offset: Default Value: Access: Size: 1E-1Fh 02A0h RO, R/WC 16 bits
SSTS1 is a 16-bit status register that reports the occurrence of error conditions associated with secondary side (i.e., PCI_B/AGP side) of the virtual PCI-to-PCI bridge in the GMCH.
Bit Detected Parity Error (DPE)--R/WC. 15 0 = No parity error detected. 1 = GMCH detected a parity error in the address or data phase of PCI_B/AGP bus transactions. NOTE: Software clears this bit by writing a 1 to it. 14 Received System Error (RSE)--RO. Hardwired to 0. GMCH does not have a SERR# signal pin on the AGP interface. Received Master Abort Status (RMAS)--R/WC. 13 0 = No master abort termination. 1 = GMCH terminated a Host-to-PCI_B/AGP with an unexpected master abort. NOTE: Software clears this bit by writing a 1 to it. Received Target Abort Status (RTAS)--R/WC. 12 0 = No target abort termination. 1 = GMCH-initiated transaction on PCI_B/AGP is terminated with a target abort. NOTE: Software clears this bit by writing a 1 to it. 11 10:9 8 7 6 5 4:0 Signaled Target Abort Status (STAS)--RO. Hardwired to 0. GMCH does not generate target abort on PCI_B/AGP. DEVSEL# Timing (DEVT)--RO. This 2-bit field indicates the timing of the DEVSEL# signal when the GMCH responds as a target on PCI_B/AGP. This field is hardwired to 01b (medium) to indicate the time when a valid DEVSEL# can be sampled by the initiator of the PCI cycle. Master Data Parity Error Detected (DPD)--RO. Hardwired to 0. GMCH does not implement G_PERR# signal on PCI_B. Fast Back-to-Back (FB2B)--RO. Hardwired to 1. GMCH as a target supports fast back-to-back transactions on PCI_B/AGP. Reserved. 66/60 MHz capability (CAP66)--RO. Hardwired to 1 to indicate that the AGP/PCI_B bus is capable of 66 MHz operation. Reserved. Descriptions
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Register Description
3.6.17
MBASE1--Memory Base Address Register (Device 1)
Address Offset: Default Value: Access: Size: 20-21h FFF0h RO, R/W 16 bits
This register controls the processor-to-PCI_B non-prefetchable memory access routing based on the following formula:
MEMORY_BASE address MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32-bit address. The bottom 4 bits of this register are read only and return zeroes when read. This register must be initialized by the configuration software. For the purpose of address decode, address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory address range will be aligned to a 1-MB boundary.
Bit 15:4 3:0 Descriptions Memory Address Base (MBASE)-- R/W. This field corresponds to A[31:20] of the lower limit of the memory range that will be passed by the Device 1 bridge to AGP/PCI_B. Reserved.
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Register Description
3.6.18
MLIMIT1--Memory Limit Address Register (Device 1)
Address Offset: Default Value: Access: Size: 22-23h 0000h RO, R/W 16 bits
This register controls the processor-to-PCI_B non-prefetchable memory access routing based on the following formula:
MEMORY_BASE address MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32-bit address. The bottom 4 bits of this register are read only and return zeroes when read. This register must be initialized by the configuration software. For the purpose of address decode, address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory address range will be at the top of a 1-MB aligned memory block. Note: Memory range covered by MBASE and MLIMIT registers are used to map non-prefetchable PCI_B/AGP address ranges (typically, where control/status memory-mapped I/O data structures of the graphics controller will reside) and PMBASE and PMLIMIT are used to map prefetchable address ranges (typically, graphics local memory). This segregation allows application of USWC space attribute to be performed in a true plug-and-play manner to the prefetchable address range for improved Processor-AGP memory access performance. Configuration software is responsible for programming all address range registers (prefetchable, non-prefetchable) with the values that provide exclusive address ranges (i.e., prevent overlap with each other and/or with the ranges covered with the main memory). There is no provision in the GMCH hardware to enforce prevention of overlap and operations of the system in the case of overlap are not guaranteed.
Bit 15:4 3:0 Descriptions Memory Address Limit (MLIMIT)--R/W. This field corresponds to A[31:20] of the memory address that corresponds to the upper limit of the range of memory accesses that will be passed by the Device 1 bridge to AGP/PCI_B. Reserved.
Note:
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Register Description
3.6.19
PMBASE1--Prefetchable Memory Base Address Register (Device 1)
Address Offset: Default Value: Access: Size: 24-25h FFF0h RO, R/W 16 bits
This register controls the processor-to-PCI_B prefetchable memory accesses routing based on the following formula:
PREFETCHABLE_MEMORY_BASE address PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32-bit address. The bottom 4 bits of this register are read only and return zeros when read. This register must be initialized by the configuration software. For the purpose of address decode, address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory address range will be aligned to a 1-MB boundary.
Bit 15:4 3:0 Descriptions Prefetchable Memory Address Base (PMBASE)--R/W. This field corresponds to A[31:20] of the lower limit of the address range passed by bridge Device 1 across AGP/PCI_B. Reserved.
3.6.20
PMLIMIT1--Prefetchable Memory Limit Address Register (Device 1)
Address Offset: Default Value: Access: Size: 26-27h 0000h RO, R/W 16 bits
This register controls the processor-to-PCI_B prefetchable memory accesses routing based on the following formula:
PREFETCHABLE_MEMORY_BASE address PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32-bit address. The bottom 4 bits of this register are read only and return zeroes when read. This register must be initialized by the configuration software. For the purpose of address decode, address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory address range will be at the top of a 1-MB aligned memory block. Note that prefetchable memory range is supported to allow segregation by the configuration software between the memory ranges that must be defined as UC and the ones that can be designated as a USWC (i.e., prefetchable) from the processor perspective.
Bit 15:4 3:0 Descriptions Prefetchable Memory Address Limit (PMLIMIT)--R/W. This field corresponds to A[31:20] of the upper limit of the address range passed by bridge Device 1 across AGP/PCI_B. Reserved.
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Register Description
3.6.21
BCTRL1--Bridge Control Register (Device 1)
Address Offset: Default Value: Access: Size: 3Eh 00h RO, R/W 8 bits
This register provides extensions to the PCICMD1 register that are specific to PCI-to-PCI bridges. The BCTRL1 provides additional control for the secondary interface (i.e., PCI_B/AGP) as well as some bits that affect the overall behavior of the virtual PCI-to-PCI bridge in the GMCH (e.g., VGA compatible address ranges mapping).
Bit 7 6 5 4 Descriptions Fast Back-to-Back Enable (FB2BEN)--RO. Hardwired to 0. GMCH does not generate fast backto-back cycles as a master on AGP. Secondary Bus Reset (SRESET)--RO. Hardwired to 0. GMCH does not support generation of reset via this bit on the AGP. Master Abort Mode (MAMODE)--RO. Hardwired to 0. Thus, when acting as a master on AGP/ PCI_B, the GMCH will discard writes and return all 1s during reads when a master abort occurs. Reserved. VGA Enable (VGAEN)--R/W. This bit controls the routing of processor-initiated transactions targeting VGA compatible I/O and memory address ranges. This bit works in conjunction with the GMCHCFG[MDAP] bit (offset C6h) as described in Table 9. 0 = Disable 1 = Enable ISA Enable (ISAEN)--R/W. This bit modifies the response by the GMCH to an I/O access issued by the processor that target ISA I/O addresses. This applies only to I/O addresses that are enabled by the IOBASE and IOLIMIT registers. 2 0 =All addresses defined by the IOBASE and IOLIMIT for processor I/O transactions are mapped to PCI_B/AGP. (default) 1 =The GMCH does not forward to PCI_B/AGP any I/O transactions addressing the last 768 bytes in each 1-KB block, even if the addresses are within the range defined by the IOBASE and IOLIMIT registers. Instead of going to PCI_B/AGP these cycles are forwarded to HI where they can be subtractively or positively claimed by the ISA bridge. 1 SERR Enable (SERREN)--RO. Hardwired to 0. This bit normally controls forwarding SERR# on the secondary interface to the primary interface. The GMCH does not support the SERR# signal on the AGP/PCI_B bus. Parity Error Response Enable (PEREN)--R/W. This bit controls the GMCH's response to data phase parity errors on PCI_B/AGP. G_PERR# is not implemented by the GMCH. 0 0 =Disable. Address and data parity errors on PCI_B/AGP are not reported via the GMCH HI SERR messaging mechanism. Other types of error conditions can still be signaled via SERR messaging independent of this bit's state. 1 =Enable. Address and data parity errors detected on PCI_B are reported via the HI SERR messaging mechanism, if further enabled by SERRE1.
3
The bit field definitions for VGAEN and MDAP are detailed in Table 9. Table 9. VGAEN and MDAP Field Definitions
VGAEN 0 0 1 1 MDAP 0 1 0 1 Description All References to MDA and VGA space are routed to HI. Illegal combination. All VGA references are routed to this bus. MDA references are routed to HI. All VGA references are routed to this bus. MDA references are routed to HI.
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Register Description
3.6.22
ERRCMD1--Error Command Register (Device 1)
Address Offset: Default Value: Access: Size: 40h 00h RO, R/W 8 bits
Bit 7:1 Reserved.
Descriptions
SERR on Receiving Target Abort (SERTA)--R/W. 0 0 =The GMCH does not assert a SERR message upon receipt of a target abort on PCI_B. SERR messaging for Device 1 is globally enabled in the PCICMD1 register. 1 =The GMCH generates a SERR message over HI upon receiving a target abort on PCI_B.
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Register Description
3.7
Integrated Graphics Device Registers (Device 2)
Function 0 can be VGA compatible or not; this is selected through GC[bit 1] (offset 52, Device 0). This section contains the Integrated Graphics Device PCI configuration registers listed in order of ascending offset address. The register address map is shown in Table 10.
Table 10. Integrated Graphics Device PCI Register Address Map (Device 2)
Address Offset 00-01h 02-03h 04-05h 06-07h 08h 09-0Bh 0Ch 0Dh 0Eh 0Fh 10-13h 14-17h 18-1Bh 1C-2Bh 2C-2Dh 2E-2Fh 30-33h 34h 35-3Bh 3Ch 3Dh 3Eh 3Fh 40-CFh D0-D1h D2-D3h D4-D5h D6-DFh E0-E1h E2-FFh Register Symbol VID2 DID2 PCICMD2 PCISTS2 RID2 CC CLS MLT2 HDR2 -- GMADR MMADR IOBAR -- SVID2 SID2 ROMADR CAPPOINT -- INTRLINE INTRPIN MINGNT MAXLAT -- PMCAPID PMCAP PMCS -- SWSMI -- Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Class Code Cache Line Size Master Latency Timer Header Type Intel Reserved Graphics Memory Range Address Memory-Mapped Range Address IO Decode Reserved Subsystem Vendor Identification Subsystem Identification Video BIOS ROM Base Address Capabilities Pointer Reserved Interrupt Line Interrupt Pin Minimum Grant Maximum Latency Intel Reserved Power Management Capabilities ID Power Management Capabilities Power Management Control Intel Reserved Software SMI Interface Intel Reserved Default Value 8086h 2572h 0000h 0090h See register description 030000h 00h 00h 00h -- 00000008h 00000000h 00000000h -- 0000h 0000h 00000000h D0h -- 00h 01h 00h 00h 00h 0001h 0021h 0000h -- 0000h -- Access RO RO RO,R/W RO,R/WC RO RO RO RO RO -- R/W,RO R/W,RO R/W -- R/WO R/WO RO RO -- R/W, RO RO RO RO -- RO RO R/W,RO -- R/W --
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Register Description
3.7.1
VID2--Vendor Identification Register (Device 2)
Address Offset: Default Value: Access: Size: 00h-01h 8086h RO 16 bits
The VID register contains the vendor identification number. This 16-bit register, combined with the Device Identification register, uniquely identify any PCI device.
Bit 15:0 Description Vendor Identification Number--RO. This is a 16-bit value assigned to Intel.
3.7.2
DID2--Device Identification Register (Device 2)
Address Offset: Default Value: Access: Size: 02h-03h 2572h RO 16 bits
This 16-bit register combined with the Vendor Identification register uniquely identifies any PCI device.
Bit 15:0 Description Device Identification Number--RO. This is a 16-bit value assigned to the GMCH IGD.
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Register Description
3.7.3
PCICMD2--PCI Command Register (Device 2)
Address Offset: Default: Access: Size: 04h-05h 0000h RO, R/W 16 bits
This 16-bit register provides basic control over the IGD's ability to respond to PCI cycles. The PCICMD register in the IGD disables the IGD PCI compliant master accesses to main memory.
Bit 15:10 9 8 7 6 5 4 3 2 Reserved. Fast Back-to-Back (FB2B)RO. Hardwired to 0. SERR# Enable (SERRE) --RO. Hardwired to 0. Address/Data SteppingRO. Hardwired to 0. Parity Error Enable (PERRE)RO. Hardwired to 0. Since the IGD belongs to the category of devices that does not corrupt programs or data in system memory or hard drives, the IGD ignores any parity error that it detects and continues with normal operation. Video Palette Snooping (VPS)RO. Hardwired to 0 to disable snooping. Memory Write and Invalidate Enable (MWIE)RO. Hardwired to 0. The IGD does not support memory write and invalidate commands. Special Cycle Enable (SCE)RO. Hardwired to 0. The IGD ignores Special cycles. Bus Master Enable (BME)R/W. 0 = Disable IGD bus mastering. 1 = Enable the IGD to function as a PCI compliant master. Memory Access Enable (MAE)R/W. This bit controls the IGD's response to memory space accesses. 0 = Disable (default). 1 = Enable. I/O Access Enable (IOAE)R/W. This bit controls the IGD's response to I/O space accesses. 0 0 = Disable (default). 1 = Enable. Description
1
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Register Description
3.7.4
PCISTS2--PCI Status Register (Device 2)
Address Offset: Default Value: Access: Size: 06h-07h 0090h RO, R/WC 16 bits
PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master abort and PCI compliant target abort. PCISTS also indicates the DEVSEL# timing that has been set by the IGD.
Bit 15 14 13 12 11 10:9 8 7 6 5 4 3:0 Description Detected Parity Error (DPE)RO. Hardwired to 0. The IGD does not detect parity. Signaled System Error (SSE)RO. Hardwired to 0. The IGD never asserts SERR#. Received Master Abort Status (RMAS)RO. Hardwired to 0. The IGD never gets a Master Abort. Received Target Abort Status (RTAS)RO. Hardwired to 0. The IGD never gets a Target Abort. Signaled Target Abort Status (STAS)--RO. Hardwired to 0. The IGD does not use target abort semantics. DEVSEL# Timing (DEVT) --RO. Hardwired to 00; Not applicable. Data Parity Detected (DPD) RO. Hardwired to 0. Parity Error Response is hardwired to disabled (and the IGD does not do any parity detection). Fast Back-to-Back (FB2B)--RO. Hardwired to 1. The IGD accepts fast back-to-back when the transactions are not to the same agent. User Defined Format (UDF)--RO. Hardwired to 0. 66 MHz PCI Capable (66C).--RO. Hardwired to 0; Not applicable. CAP LIST--RO. Hardwired to 1 to indicate that the register at 34h provides an offset into the function's PCI Configuration space containing a pointer to the location of the first item in the list. Reserved.
3.7.5
RID2--Revision Identification Register (Device 2)
Address Offset: Default Value: Access: Size: 08h See table below RO 8 bits
This register contains the revision number of the IGD.
Bit 7:0 Description Revision Identification Number--RO. This is an 8-bit value that indicates the revision identification number for the IGD. 02h = A-2 Stepping
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Register Description
3.7.6
CC--Class Code Register (Device 2)
Address Offset: Default Value: Access: Size: 09h-0Bh 030000h RO 24 bits
This register contains the device programming interface information related to the Sub-Class Code and Base Class Code definition for the IGD. This register also contains the Base Class Code and the function sub-class in relation to the Base Class Code.
Bit 23:16 Base Class Code (BASEC)--RO. 03 = Display controller Sub-Class Code (SCC)--RO. 15:8 00h = VGA compatible 80h = Non-VGA based on device 0 GCBIT 1 as well as Device 0 GC Register Bits 6:4 7:0 Programming Interface (PI)--RO. 00h = Display controller. Description
3.7.7
CLS--Cache Line Size Register (Device 2)
Address Offset: Default Value: Access: Size: 0Ch 00h RO 8 bits
The IGD does not support this register as a PCI slave.
Bit 7:0 Description Cache Line Size (CLS)--RO. Hardwired to 00h. The IGD, as a PCI compliant master, does not use the memory write and Invalidate command and, in general, does not perform operations based on cache line size.
3.7.8
MLT2--Master Latency Timer Register (Device 2)
Address Offset: Default Value: Access: Size: 0Dh 00h RO 8 bits
The IGD does not support the programmability of the master latency timer because it does not perform bursts.
Bit 7:0 Description Master Latency Timer Count Value--RO. Hardwired to 00h.
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Register Description
3.7.9
HDR2--Header Type Register (Device 2)
Address Offset: Default Value: Access: Size: 0Eh 00h RO 8 bits
This register contains the Header Type of the IGD.
Bit 7:0 Description Header Code (H)--RO. This is an 8-bit value that indicates the Header Code for the IGD. 00h = Single function device with a type 0 configuration space format.
3.7.10
GMADR--Graphics Memory Range Address Register (Device 2)
Address Offset: Default Value: Access: Size: 10-13h 00000008h R/W, RO 32 bits
This register requests allocation for the IGD graphics memory. The allocation is for 128 MB and the base address is defined by bits [31:27].
Bit 31:27 26 25:4 3 2:1 0 Description Memory Base AddressR/W. Set by the OS, these bits correspond to address signals [31:26]. 128MB Address Mask--RO. Hardwired to 0 to indicate 128-MB address space. Address Mask--RO. Hardwired to 0s to indicate (at least) a 32-MB address range. Prefetchable Memory--RO. Hardwired to 1 to enable prefetching. Memory Type--RO. Hardwired to 00 to indicate 32-bit address. Memory/IO Space--RO. Hardwired to 0 to indicate memory space.
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Register Description
3.7.11
MMADR--Memory-Mapped Range Address Register (Device 2)
Address Offset: Default Value: Access: Size: 14-17h 00000000h R/W, RO 32 bits
This register requests allocation for the IGD registers and instruction ports. The allocation is for 512 KB and the base address is defined by bits [31:19].
Bit 31:19 18:4 3 2:1 0 Description Memory Base AddressR/W. Set by the OS, these bits correspond to address signals [31:19]. Address MaskRO. Hardwired to 0s to indicate 512-KB address range. Prefetchable MemoryRO. Hardwired to 0 to prevent prefetching. Memory TypeRO. Hardwired to 00 to indicate 32-bit address. Memory / IO SpaceRO. Hardwired to 0 to indicate memory space.
3.7.12
IOBAR--I/O Decode Register (Device 2)
Address Offset: Default Value: Access: Size: 18-1Bh 00000001h R/W, RO 32 bits
This register provides the base offset of the I/O registers within Device 2. Bits 15:3 are programmable allowing the I/O base to be located anywhere in 16-bit I/O address space. Bits 2:1 are fixed and return 0s; bit 0 is hardwired to 1 indicating that 8 bytes of I/O space are decoded. Access to the 8 bytes of I/O space is allowed in power management (PM) state D0 when the I/O Enable bit (PCICMD2 bit 0) is set. Access is disallowed in PM states D1-D3 if:
* the I/O Enable bit is 0 * Device 2 is turned off * Internal graphics is disabled thru the fuse mechanisms.
Note that access to the IOBAR register is independent of VGA functionality in Device 2. Also, note that this mechanism is available only through function 0 of Device 2. If accesses to the IOBAR is allowed, the GMCH claims all 8-, 16- or 32-bit I/O cycles from the processor that falls within the 8 bytes claimed.
Bit 31:16 15:3 2:1 0 Reserved. Read as 0. I/O Base Address--R/W. This field is set by the OS. These bits correspond to address signals 15:3. They provide the 16-bit I/O base address for the I/O registers. Memory TypeRO. Hardwired to 00 to indicate 32-bit address. I/O SpaceRO. Hardwired to 1 to indicate I/O space. Description
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Register Description
3.7.13
SVID2--Subsystem Vendor Identification Register (Device 2)
Address Offset: Default Value: Access: Size:
Bit 15:0
2C-2Dh 0000h R/WO 16 bit
Description
Subsystem Vendor ID--R/WO. This value is used to identify the vendor of the subsystem. This register should be programmed by BIOS during boot-up. Once written, this register becomes read only. This register can only be cleared by a Reset.
3.7.14
SID2--Subsystem Identification Register (Device 2)
Address Offset: Default Value: Access: Size:
Bit 15:0
2E-2Fh 0000h R/WO 16 bits
Description
Subsystem Identification--R/WO. This value is used to identify a particular subsystem. This field should be programmed by BIOS during boot-up. Once written, this register becomes read only. This register can only be cleared by a Reset.
3.7.15
ROMADR--Video BIOS ROM Base Address Registers (Device 2)
Address Offset: Default Value: Access: Size: 30-33h 00000000h RO 32 bits
The IGD does not use a separate BIOS ROM; therefore, this register is hardwired to zeros.
Bit 31:18 17:11 10:1 0 Description ROM Base Address--RO. Hardwired to 0s. Address MaskRO. Hardwired to 0s to indicate 256-KB address range. Reserved. Hardwired to 0s. ROM BIOS Enable--RO. 0 = ROM not accessible.
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Register Description
3.7.16
CAPPOINT--Capabilities Pointer Register (Device 2)
Address Offset: Default Value: Access: Size:
Bit 7:0
34h D0h RO 8 bits
Description
Capabilities Pointer Value--RO. This field contains an offset into the function's PCI configuration space for the first item in the New Capabilities Linked List, the ACPI registers at address D0h.
3.7.17
INTRLINE--Interrupt Line Register (Device 2)
Address Offset: Default Value: Access: Size:
Bit
3Ch 00h R/W 8 bits
Description
7:0
Interrupt Connection--R/W. This field is used to communicate interrupt line routing information. POST software writes the routing information into this register as it initializes and configures the system. The value in this register indicates which input of the system interrupt controller that the device's interrupt pin is connected to. This register is needed for Plug-N-Play software. Settings of this register field has no effect on GMCH operation as there is no hardware functionality associated with this register, other than the hardware implementation of the R/W register itself.
3.7.18
INTRPIN--Interrupt Pin Register (Device 2)
Address Offset: Default Value: Access: Size:
Bit 7:0
3Dh 01h RO 8 bits
Description
Interrupt Pin--RO. As a single function device, the IGD specifies INTA# as its interrupt pin. 01h = INTA#.
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Register Description
3.7.19
MINGNT--Minimum Grant Register (Device 2)
Address Offset: Default Value: Access: Size:
Bit 7:0
3Eh 00h RO 8 bits
Description
Minimum Grant Value--RO. Hardwired to 00h. The IGD does not burst as a PCI compliant master.
3.7.20
MAXLAT--Maximum Latency Register (Device 2)
Address Offset: Default Value: Access: Size:
Bit 7:0
3Fh 00h RO 8 bits
Description
Maximum Latency Value--RO. Hardwired to 00h. The IGD has no specific requirements for how often it needs to access the PCI bus.
3.7.21
PMCAPID--Power Management Capabilities Identification Register (Device 2)
Address Offset: Default Value: Access: Size:
Bit 15:8 7:0
D0h-D1h 0001h RO 16 bits
Description
NEXT_PTR--RO. This field contains a pointer to next item in the capabilities list. This is the final capability in the list and must be set to 00h. CAP_ID--RO. SIG defines this ID as 01h for power management.
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Register Description
3.7.22
PMCAP--Power Management Capabilities Register (Device 2)
Address Offset: Default Value: Access: Size:
Bit 15:11 10 9 8:6 5 4 3 2:0
D2h-D3h 0021h RO 16 bits
Description
PME Support--RO. Hardwired to 0s. This field indicates the power states in which the IGD may assert PME#. It is hardwired to 0 to indicate that the IGD does not assert the PME# signal. D2--RO. Hardwired to 0. The D2 power management state is not supported. D1--RO. Hardwired to 0. The D1 power management state is not supported. Reserved. Device Specific Initialization (DSI)--RO. Hardwired to 1 to indicate that special initialization of the IGD is required before generic class device driver is to use it. Auxiliary Power Source--RO. Hardwired to 0. PME Clock--RO. Hardwired to 0. IGD does not support PME# generation. Version--RO. Hardwired to 001b to indicate there are 4 bytes of power management registers implemented.
3.7.23
PMCS--Power Management Control/Status Register (Device 2)
Address Offset: Default Value: Access: Size:
Bit 15 14:13 12:9 8 7:2
D4h-D5h 0000h R/W, RO 16 bits
Description
PME_Status--RO. Hardwired to 0. IGD does not support PME# generation from D3 (cold). Data Scale (Reserved)--RO. Hardwired to 00. The IGD does not support data register. Data_Select (Reserved)--RO. Hardwired to 0h. The IGD does not support data register. PME_EnRO. Hardwired to 0. PME# assertion from D3 (cold) is disabled. Reserved. PowerStateR/W. This field indicates the current power state of the IGD and can be used to set the IGD into a new power state. If software attempts to write an unsupported state to this field, write operation must complete normally on the bus, but the data is discarded and no state change occurs.
1:0
00 = D0 (Default) 01 = D1 (Not Supported- Writes will be blocked and will return the previous value.) 10 = D2 (Not Supported- Writes will be blocked and will return the previous value.) 11 = D3
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Register Description
3.7.24
SWSMI--Software SMI Interface Register (Device 2)
Address Offset: Default Value: Size: Access:
Bit 15:1 0
E0h-E1h 0000h 16 bits R/W
Description
SMI Message Passing Field--R/W. These bits are R/W bits that are used to pass messages between Graphics software and the System BIOS. These bits have no functional impact on the GMCH. (default = 0s) Software SMI Trigger--R/W. When this bit transitions from 0 to 1, the GMCH will generate an SMI message over HI. The SMI handler (software) must clear this bit by writing a 0 to it. (default = 0).
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Register Description
3.8
PCI-to-CSA Bridge Registers (Device 3)
This device is the virtual PCI-to-CSA bridge. This section contains the PCI configuration registers listed in order of ascending offset address. Table 11 provides the register address map for this device.
Table 11. PCI-to-CSA Bridge Configuration Register Address Map (Device 3)
Address Offset 00-01h 02-03h 04-05h 06-07h 08h 09 0Ah 0Bh 0Ch 0Dh 0Eh 0F-17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1E-1Fh 20-21h 22-23h 24-25h 26-27h 28-3Dh 3Eh 3Fh 40h 41-4Fh 50-53h 54-FFh Register Symbol VID3 DID3 PCICMD3 PCISTS3 RID3 -- SUBC3 BCC3 -- MLT3 HDR3 -- PBUSN3 SBUSN3 SUBUSN3 SMLT3 IOBASE3 IOLIMIT3 SSTS3 MBASE3 MLIMIT3 PMBASE3 PMLIMIT3 -- BCTRL3 -- ERRCMD3 -- CSACNTRL -- Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Reserved Sub-Class Code Base Class Code Reserved Master Latency Timer Header Type Reserved Primary Bus Number Secondary Bus Number Subordinate Bus Number Secondary Bus Master Latency Timer I/O Base Address I/O Limit Address Secondary Status Memory Base Address Memory Limit Address Prefetchable Memory Base Limit Address Prefetchable Memory Limit Address Reserved Bridge Control Reserved Error Command Reserved CSA Control Intel Reserved Default Value 8086h 2573h 0000h 00A0h See register description -- 04h 06h -- 00h 01h -- 00h 00h 00h 00h F0h 00h 02A0h FFF0h 0000h FFF0h 0000h -- 00h -- 00h -- 0E04 2802h -- Access RO RO RO,R/W RO,R/WC RO -- RO RO -- RO,R/W RO -- R/W R/W R/W RO,R/W RO,R/W RO,R/W RO,R/WC RO,R/W RO,R/W RO,R/W RO,R/W -- RO,R/W -- RO,R/W -- RO,R/W --
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Register Description
3.8.1
VID3--Vendor Identification Register (Device 3)
Address Offset: Default Value: Access: Size: 00h-01h 8086h RO 16 bits
The VID register contains the vendor identification number. This 16-bit register, combined with the Device Identification register, uniquely identify any PCI device.
Bit 15:0 Description Vendor Identification Number--RO. This is a 16-bit value assigned to Intel.
3.8.2
DID3--Device Identification Register (Device 3)
Address Offset: Default Value: Access: Size: 02h-03h 2573h RO 16 bits
This 16-bit register, combined with the Vendor Identification register, uniquely identifies any PCI device.
Bit 15:0 Description Device Identification Number--RO. This is a 16-bit value assigned to the GMCH Device 3.
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Register Description
3.8.3
PCICMD3--PCI Command Register (Device 3)
Address Offset: Default: Access: Size:
Bit 15:10 9 Reserved. Fast Back-to-Back (FB2B)RO. Hardwired to 0. SERR# Enable (SERRE) R/W. This bit is a global enable bit for Device 3 SERR messaging. The GMCH communicates the SERR# condition by sending a SERR message to the ICH5. 8 0 = Disable. The SERR message is not generated by the GMCH for Device 3. 1 = Enable. The GMCH is enabled to generate SERR messages over HI for specific Device 3 error conditions that are individually enabled in the BCTRL3 register. The error status is reported in the PCISTS3 register. Address/Data Stepping (ADSTEP)RO. Hardwired to 0. Parity Error Enable (PERRE) RO. Hardwired to 0. Parity checking is not supported on the primary side of this device. Reserved. Memory Write and Invalidate Enable (MWIE)RO. Hardwired to 0. Special Cycle Enable (SCE)RO. Hardwired to 0. Bus Master Enable (BME)R/W. This bit is not functional. It is a R/W bit for compatibility with compliance testing software. Memory Access Enable (MAE)R/W. This bit must be set to 1 to enable the memory and prefetchable memory address ranges defined in the MBASE3, MLIMIT3, PMBASE3, and PMLIMIT3 registers. 0 = Disable (default). 1 = Enable. I/O Access Enable (IOAE)R/W. This bit must be set to 1 to enable the I/O address range defined in the IOBASE3 and IOLIMIT3 registers 0 = Disable (default). 1 = Enable.
04h-05h 0000h RO, R/W 16 bits
Description
7 6 5 4 3 2
1
0
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Register Description
3.8.4
PCISTS3--PCI Status Register (Device 3)
Address Offset: Default Value: Access: Size: 06h-07h 00A0h RO, R/WC 16 bits
PCISTS3 is a 16-bit status register that reports the occurrence of error conditions associated with primary side of the virtual PCI-to-CSA bridge in the GMCH. Note: For R/WC bits, software must write a 1 to clear bits that are set.
Bit 15 Description Detected Parity Error (DPE)RO. Hardwired to 0. Parity is not supported on the primary side of this device. Signaled System Error (SSE)R/WC. 14 0 = No SERR message generated by GMCH Device 3 over HI. 1 = GMCH Device 3 generated a SERR message over HI for any enabled Device 3 error condition. Device 3 error conditions are enabled in the ERRCMD, PCICMD3, and BCTRL3 registers. Device 3 error flags are read/reset from the ERRSTS and SSTS3 register. Received Master Abort Status (RMAS)RO. Hardwired to 0. The concept of a master abort does not exist on the primary side of this device. Received Target Abort Status (RTAS)RO. Hardwired to 0. The concept of a target abort does not exist on the primary side of this device. Signaled Target Abort Status (STAS)--RO. Hardwired to 0. The concept of a target abort does not exist on primary side of this device. DEVSEL# Timing (DEVT)--RO. The Hardwired to 00b. GMCH does not support subtractive decoding devices on bus 0. The value 00b indicates that Device 3 uses the fastest possible decode. Data Parity Detected (DPD)RO. Hardwired to 0. Parity Error Response is hardwired to disabled (and the GMCH does not support any parity detection on the primary side of this device). Fast Back-to-Back (FB2B)--RO. Hardwired to 1. The interface always supports fast back-to-back writes. Reserved. 66/60 MHz PCI Capable (CAP66)--RO. Hardwired to 1. CSA is 66 MHz capable. Reserved.
13 12 11 10:9 8 7 6 5 4:0
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Register Description
3.8.5
RID3--Revision Identification Register (Device 3)
Address Offset: Default Value: Access: Size: 08h See table below RO 8 bits
This register contains the revision number of the GMCH Device 3.
Bit 7:0 Description Revision Identification Number--RO. This is an 8-bit value that indicates the revision identification number for the GMCH Device 3. It is always the same as the value in the RID register. 02h = A-2 Stepping
3.8.6
SUBC3--Class Code Register (Device 3)
Address Offset: Default Value: Access: Size: 0Ah 04h RO 8 bits
This register contains the Sub-Class Code for the GMCH Device 3.
Bit 7:0 Description Sub-Class Code (SUBC)--RO. This is an 8-bit value that indicates the category of Bridge for the GMCH Device 3. 04h = PCI-to-PCI bridge.
3.8.7
BCC3--Base Class Code Register (Device 3)
Address Offset: Default Value: Access: Size: 0Bh 06h RO 8 bits
This register contains the Base Class Code of the GMCH Device 3.
Bit 7:0 Description Base Class Code (BASEC)--RO. This is an 8-bit value that indicates the Base Class Code for the GMCH Device 3. 06h = Bridge device.
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Register Description
3.8.8
MLT3--Master Latency Timer Register (Device 3)
Address Offset: Default Value: Access: Size: 0Dh 00h RO, RW 8 bits
This functionality is not applicable. It is described here since these bits should be implemented as a read/write to prevent standard PCI-to-PCI bridge configuration software from getting "confused."
Bit 7:3 2:0 Description Scratchpad MLT (NA7:3)--R/W. These bits return the value that was last written; however, they have no internal function and are implemented as a Scratchpad to avoid confusing software. Reserved.
3.8.9
HDR3--Header Type Register (Device 3)
Address Offset: Default Value: Access: Size: 0Eh 01h RO 8 bits
This register identifies the header layout of the configuration space.
Bit 7:0 Header Type Register (HDR)--RO. 01h = GMCH Device 3 is a single function device with bridge header layout. Description
3.8.10
PBUSN3--Primary Bus Number Register (Device 3)
Address Offset: Default Value: Access: Size: 18h 00h RO 8 bits
This register identifies that virtual PCI-to-PCI bridge is connected to bus 0.
Bit 7:0 Description Primary Bus Number (BUSN)--RO. Configuration software typcially programs this field with the number of the bus on the primary side of the bridge. Since Device 3 is an internal device and its primary bus is always 0, these bits are read only and are hardwired to 00h.
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Register Description
3.8.11
SBUSN3--Secondary Bus Number Register (Device 3)
Address Offset: Default Value: Access: Size: 19h 00h R/W 8 bits
This register identifies the bus number assigned to the second bus side of the virtual PCI-to-PCI bridge (i.e., CSA). This number is programmed by the PCI configuration software to allow mapping of configuration cycles to CSA.
Bit 7:0 Description Secondary Bus Number (BUSN)--R/W. This field is programmed by configuration software with the bus number assigned to CSA.
3.8.12
SMLT3--Secondary Bus Master Latency Timer Register (Device 3)
Address Offset: Default Value: Access: Size:
Bit 7:0 Reserved.
1Bh 00h RO 8 bits
Description
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Register Description
3.8.13
IOBASE3--I/O Base Address Register (Device 3)
Address Offset: Default Value: Access: Size: 1Ch F0h RO, R/W 8 bits
This register controls the processor-to-CSA I/O access routing based on the following formula:
IO_BASE address IO_LIMIT
Only the upper 4 bits are programmable. For the purpose of address decode, address bits A[11:0] are treated as 0. Thus, the bottom of the defined I/O address range will be aligned to a 4-KB boundary.
Bit 7:4 3:0 Description I/O Address Base (IOBASE)-- R/W. This field corresponds to A[15:12] of the I/O addresses passed by bridge 1 to CSA. Reserved.
3.8.14
IOLIMIT3--I/O Limit Address Register (Device 3)
Address Offset: Default Value: Access: Size: 1Dh 00h RO, RW 8 bits
This register controls the processor-to-CSA I/O access routing based on the following formula:
IO_BASE address IO_LIMIT
Only the upper 4 bits are programmable. For the purpose of address decode, address bits A[11:0] are assumed to be FFFh. Thus, the top of the defined I/O address range will be at the top of a 4-KB aligned address block.
Bit 7:4 3:0 Description I/O Address Limit (IOLIMIT)--R/W. This field corresponds to A[15:12] of the I/O address limit of Device 3. Devices between this upper limit and IOBASE3 will be passed to CSA. Reserved.
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Register Description
3.8.15
SSTS3--Secondary Status Register (Device 3)
Address Offset: Default Value: Access: Size: 1E-1Fh 02A0h RO, RWC 16 bits
SSTS3 is a 16 bit status register that reports the occurrence of error conditions associated with the secondary side (i.e., CSA side) of the virtual PCI-to-PCI bridge in the GMCH. Note: For R/WC bits, software must write a 1 to clear bits that are set.
Bit 15 14 Description Detected Parity Error (DPE)-- RO. Hardwired to 0. Parity is not supported on the CSA interface. Received System Error (RSE)--R/WC. 0 = No system error signalled by CSA device. 1 = CSA device signals a system error to the GMCH. Received Master Abort Status (RMAS) R/WC. 13 0 = No master abort by GMCH to terminate a Host-to-CSA transaction. 1 = GMCH terminated a Host-to-CSA transaction with an unexpected master abort. Received Target Abort Status (RTAS) R/WC. 12 0 = No target abort for GMCH-initiated transaction on CSA. 1 = GMCH-initiated transaction on CSA is terminated with a target abort. Signaled Target Abort Status (STAS)--RO. Hardwired to 0. The GMCH does not generate a target abort on CSA. DEVSEL# Timing (DEVT) --RO. Hardwired to 01b. This 2-bit field indicates the timing of the DEVSEL# signal when the GMCH responds as a target on CSA. The 01b value (medium timing) indicates the time when a valid DEVSEL# can be sampled by initiator of the PCI cycle. Master Data Parity Detected (DPD)--RO. Hardwired to 0. GMCH does not implement G_PERR# signal on CSA. Fast Back-to-Back (FB2B)--RO. Hardwired to 1. GMCH, as a target, supports fast back-to-back transactions on CSA. Reserved. 66/60 MHz PCI Capable (CAP66)--RO. Hardwired to 1. CSA is 66 MHz capable. Reserved.
11 10:9 8 7 6 5 4:0
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Register Description
3.8.16
MBASE3--Memory Base Address Register (Device 3)
Address Offset: Default Value: Access: Size: 20-21h FFF0h RO, RW 16 bits
This register controls the processor-to-CSA non-prefetchable memory access routing based on the following formula:
MEMORY_BASE address MEMORY_LIMIT
The Upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32-bit address. The bottom 4 bits of this register are read only and return zeroes when read. This register must be initialized by the configuration software. For the purpose of address decode, address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory address range will be aligned to 1-MB boundary.
Bit 15:4 3:0 Description Memory Address Limit (MLIMIT)-- R/W. This field corresponds to A[31:20] of the lower limit of the memory range that will be passed by Device 3 bridge to CSA. Reserved.
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Register Description
3.8.17
MLIMIT3--Memory Limit Address Register (Device 3)
Address Offset: Default Value: Access: Size: 22-23h 0000h RO, R/W 16 bits
This register controls the processor-to-CSA non-prefetchable memory access routing based on the following formula:
MEMORY_BASE address MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32-bit address. The bottom 4 bits of this register are read only and return zeroes when read. This register must be initialized by the configuration software. For the purpose of address decode, address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory address range will be at the top of a 1-MB aligned memory block. Note: Memory ranges covered by the MBASE and MLIMIT registers are used to map non-prefetchable CSA address ranges (typically, where control/status memory-mapped I/O data structures of the graphics controller will reside) and the PMBASE and PMLIMIT registers are used to map prefetchable address ranges (typically, graphics local memory). This segregation allows application of USWC space attribute to be performed in a true plug-and-play manner to the prefetchable address range for improved Processor-CSA memory access performance. Configuration software is responsible for programming all address range registers (prefetchable, non-prefetchable) with the values that provide exclusive address ranges (i.e., prevent overlap with each other and/or with the ranges covered with the main memory). There is no provision in the GMCH hardware to enforce prevention of overlap and operations of the system in the case of overlap are not guaranteed.
Bit 15:4 3:0 Description Memory Address Limit (MLIMIT)--R/W. This field corresponds to A[31:20] of the memory address that corresponds to the upper limit of the range of memory accesses that will be passed by the Device 3 bridge to CSA. Reserved.
Note:
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Register Description
3.8.18
PMBASE3--Prefetchable Memory Base Address Register (Device 3)
Address Offset: Default Value: Access: Size: 24-25h FFF0h R/W, RO 16 bits
This register controls the processor-to-CSA prefetchable memory accesses routing based on the following formula:
PREFETCHABLE_MEMORY_BASE address PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32-bit address. The bottom four bits of this register are read only and return 0s when read. This register must be initialized by the configuration software. For the purpose of address decode, address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory address range will be aligned to a 1-MB boundary.
Bit 15:4 3:0 Description Prefetchable Memory Address Base (PMBASE)--R/W. This field corresponds to A[31:20] of the lower limit of the address range passed by bridge Device 3 across CSA. Reserved.
3.8.19
PMLIMIT3--Prefetchable Memory Limit Address Register (Device 3)
Address Offset: Default Value: Access: Size: 26-27h 0000h R/W, RO 16 bits
This register controls the processor to CSA prefetchable memory accesses routing based on the following formula:
PREFETCHABLE_MEMORY_BASE address PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32-bit address. The bottom 4 bits of this register are read only and return 0s when read. This register must be initialized by the configuration software. For the purpose of address decode, address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory address range will be at the top of a 1-MB aligned memory block. Note that prefetchable memory range is supported to allow segregation by the configuration software between the memory ranges that must be defined as UC and the ones that can be designated as a USWC (i.e., prefetchable) from the processor perspective.
Bit 15:4 3:0 Description Prefetchable Memory Address Limit (PMLIMIT)--R/W. This field corresponds to A[31:20] of the upper limit of the address range passed by bridge Device 3 across CSA. Reserved.
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Register Description
3.8.20
BCTRL3--Bridge Control Register (Device 3)
Address Offset: Default Value: Access: Size:
Bit 7 6 5 4
3Eh 00h R/W, RO 8 bits
Description
Fast Back-to-Back Enable (FB2BEN)--RO. Hardwired to 0. The GMCH does not generate fast back-to-back cycles as a master on AGP. Secondary Bus reset (SREST)--RO. Hardwired to 0. The GMCH does not support generation of reset via this bit on the AGP. Master Abort Mode (MAMODE)--RO. Hardwired to 0. This means that when acting as a master on CSA, the GMCH will discard writes and return all 1s during reads when a master abort occurs. Reserved. VGA Enable (VGAEN)--R/W. This bit control the routing of processor-initiated transactions targeting VGA compatible I/O and memory address ranges. This bit works in conjunction with the GMCHCFG[MDAP] bit (Device 0, offset C6h) as described in Table 12. 0 = Disable 1 = Enable ISA Enable (ISAEN)--R/W. This bit modifies the response by the GMCH to an I/O access issued by the processor that targets ISA I/O addresses. This applies only to I/O addresses that are enabled by the IOBASE and IOLIMIT registers.
3
2
0 = Disable (default). All addresses defined by the IOBASE and IOLIMIT for processor I/O transactions are mapped to CSA. 1 = Enable. The GMCH does not forward to CSA any I/O transactions addressing the last 768 bytes in each 1-KB block, even if the addresses are within the range defined by the IOBASE and IOLIMIT registers. Instead of going to CSA, these cycles are forwarded to HI where they can be subtractively or positively claimed by the ISA bridge. SERR Enable (SERREN)--RO. Hardwired to 0. This bit normally controls forwarding SERR# on the secondary interface to the primary interface. However, the GMCH does not support the SERR# signal on the CSA Bus. Parity Error Response Enable (PEREN)--RO. Hardwired to 0.
1 0
The bit field definitions for VGAEN and MDAP are detailed in Table 12. Table 12. VGAEN and MDAP Definitions
VGAEN 0 0 1 1 MDAP 0 1 0 1 Description All References to MDA and VGA space are routed to HI. Illegal combination. All VGA references are routed to this bus. MDA references are routed to HI. All VGA references are routed to this bus. MDA references are routed to HI.
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Register Description
3.8.21
ERRCMD3--Error Command Register (Device 3)
Address Offset: Default Value: Access: Size:
Bit 7:1 Reserved. SERR on Receiving Target Abort (SERTA)--R/W. 0 0 = The GMCH does not assert a SERR message upon receipt of a target abort on CSA. 1 = The GMCH generates a SERR message over CSA upon receiving a target abort on CSA. SERR messaging for Device 3 is globally enabled in the PCICMD3 register.
40h 00h R/W, RO 8 bits
Description
3.8.22
CSACNTRL--CSA Control Register (Device 3)
Address Offset: Default Value: Access: Size:
Bit 31:29 28 27:25 24:16
50-53h 0E042802h R/W, RO 32 bits
Description
First Subordinate CSA (CSA_SUB_FIRST)--R/W. This field stores the lowest subordinate CI hub number. Reserved. Last Subordinate CSA (CSA_SUB_LAST)--R/W. This field stores the highest subordinate CSA hub number. Reserved. CSA Width (CSA_WIDTH)--R/W. This field describes the used width of the data bus. 00 = 8 bit
15:14
01 = Reserved 10 = Reserved 11 = Reserved
13:0
Intel Reserved.
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Register Description
3.9
Overflow Configuration Registers (Device 6)
Device 6 is the Overflow Device for Device 0. The registers in this section are arranged in ascending order of the address offset. Table 13 provides the configuration register address map.
Table 13. Overflow Device Configuration Register Address Map (Device 6)
Address Offset 00-01h 02-03h 04-05h 06-07h 08h 09h 0Ah 0Bh 0Ch-0Dh 0Eh 0Fh 10-13h 14-2Bh 2C-2Dh 2E-2Fh 30-E6h E7-FFh Register Symbol VID6 DID6 PCICMD6 PCISTS6 RID6 -- SUBC6 BCC6 -- HDR6 -- BAR6 -- SVID6 SID6 -- -- Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Reserved Sub-Class Code Base Class Code Reserved Header Type Reserved Base Address Reserved Subsystem Vendor Identification Subsystem Identification Reserved Intel Reserved Default Value 8086h 2576h 0000h 0080h See register description -- 80h 08h -- 00h -- 00000000h -- 0000h 0000h -- -- Access RO RO RO, R/W RO RO -- RO RO -- RO -- RO -- R/WO R/WO -- --
3.9.1
VID6--Vendor Identification Register (Device 6)
Address Offset: Default Value: Access: Size: 00-01h 8086h RO 16 bits
The VID register contains the vendor identification number. This 16-bit register, combined with the Device Identification register, uniquely identifies any PCI device.
Bit 15:0 Descriptions Vendor Identification (VID)--RO. This register field contains the PCI standard identification for Intel, 8086h.
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Register Description
3.9.2
DID6--Device Identification Register (Device 6)
Address Offset: Default Value: Access: Size: 02-03h 2576h RO 16 bits
This 16-bit register, combined with the Vendor Identification register, uniquely identifies any PCI device.
Bit 15:0 Descriptions Device Identification Number (DID)--RO. This is a 16-bit value assigned to the GMCH Host-toHI Bridge, Function 0.
3.9.3
PCICMD6--PCI Command Register (Device 6)
Address Offset: Default Value: Access: Size: 04-05h 0000h RO, R/W 16 bits
Since GMCH Device 0 does not physically reside on PCI_A, many of the bits are not implemented.
Bit 15:10 9 8 7 6 5 4 3 2 Reserved. Fast Back-to-Back Enable (FB2B)--RO. Hardwired to 0. SERR Enable (SERRE)--RO. Hardwired to 0. Address/Data Stepping Enable (ADSTEP)--RO. Hardwired to 0. Parity Error Enable (PERRE)--RO. Hardwired to 0. VGA Palette Snoop Enable (VGASNOOP)--RO. Hardwired to 0. Memory Write and Invalidate Enable (MWIE)--RO. Hardwired to 0. Special Cycle Enable (SCE)--RO. Hardwired to 0. Bus Master Enable (BME)--RO. Hardwired to 0. Memory Access Enable (MAE) R/W. Set this bit to 1 to enables Device 6 memory space accesses. 0 = Disable (default). 1 = Enable. I/O Access Enable (IOAE) R/W. This bit must be set to 1 to enable the I/O address range defined in the IOBASE3 and IOLIMIT3 registers. 0 = Disable (default). 1 = Enable. Descriptions
1
0
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Register Description
3.9.4
PCISTS6--PCI Status Register (Device 6)
Address Offset: Default Value: Access: Size: 06-07h 0080h RO 16 bits
PCISTS6 is a 16-bit status register that reports the occurrence of error events on Device 6, Function 0's PCI interface. Since GMCH Device 6 does not physically reside on PCI_0, many of the bits are not implemented.
Bit 15 14 13 12 11 10:9 8 7 6:0 Descriptions Detected Parity Error (DPE)--RO. Hardwired to 0. Signaled System Error (SSE)--RO. Hardwired to 0. Received Master Abort Status (RMAS)--RO. Hardwired to 0. Received Target Abort Status (RTAS)--RO. Hardwired to 0. Signaled Target Abort Status (STAS)--RO. Hardwired to 0. DEVSEL Timing (DEVT)--RO. Hardwired to 00b. Device 6 does not physically connect to PCI_A. These bits are set to 00b (fast decode) so that optimum DEVSEL timing for PCI_A is not limited by the GMCH. Master Data Parity Error Detected (DPD)--RO. Hardwired to 0. Fast Back-to-Back (FB2B)--RO. Hardwired to 1. This indicates fast back-to-back capability; thus, the optimum setting for PCI_A is not limited by the GMCH. Reserved.
3.9.5
RID6--Revision Identification Register (Device 6)
Address Offset: Default Value: Access: Size: 08h See table below RO 8 bits
This register contains the revision number of the GMCH Device 0.
Bit 7:0 Descriptions Revision Identification Number (RID)--RO. This is an 8-bit value that indicates the revision identification number for the GMCH Device 6. This value is the same as the RID register. 02h = A-2 Stepping
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Register Description
3.9.6
SUBC6--Sub-Class Code Register (Device 6)
Address Offset: Default Value: Access: Size: 0Ah 80h RO 8 bits
This register contains the Sub-Class Code for the GMCH Device 0.
Bit 7:0 Descriptions Sub-Class Code (SUBC)--RO. This is an 8-bit value that indicates the category of Device for the GMCH Device 6. 80h = Other system peripherals.
3.9.7
BCC6--Base Class Code Register (Device 6)
Address Offset: Default Value: Access: Size: 0Bh 08h RO 8 bits
This register contains the Base Class Code for the GMCH Device 0.
Bit 7:0 Descriptions Base Class Code (BASEC)--RO. This is an 8-bit value that indicates the category of Device for the GMCH Device 6. 08h = Other system peripherals.
3.9.8
HDR6--Header Type Register (Device 6)
Address Offset: Default Value: Access: Size: 0Eh 00h RO 8 bits
This register identifies the header layout of the configuration space.
Bit 7:0 Descriptions PCI Header (HDR)--RO. This field indicates a single function device with standard header layout.
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Register Description
3.9.9
BAR6--Memory Delays Base Address Register (Device 6)
Address Offset: Default Value: Access: Size: 10-13h 00000000h RO, R/W 32 bits
This register is a standard PCI scheme to claim a memory-mapped address range. This memorymapped address range can be enabled once the relevant enable bit in the PCI command register is set to 1.
Bit 31:12 11:4 Descriptions Memory base Address--R/W. Set by the OS, these bits correspond to address signals [31:13]. Address Mask--RO. Hardwired to 00h to indicate 4-KB address range is reserved for memorymapped address space. Prefetchable--RO. This read only bit indicates the prefetchability of the requested memory address range. 3 0 = Not prefetchable. The memory range is not prefetchable and may have read side effects. 1 = Prefetchable. The memory address range is prefetchable (i.e., has no read side effects and returns all bytes on reads regardless of byte enables) and byte merging of write transactions is allowed. Memory Type (TYPE)--RO. Hardwired to 00b to indicate that address range defined by the upper bits of this register can be located anywhere in the 32-bit address space as per the PCI specification for base address registers. Memory Space Indicator (MSPACE)--RO. Hardwired to 0 to identify memory space.
2:1 0
3.9.10
SVID6--Subsystem Vendor Identification Register (Device 6)
Address Offset: Default Value: Access: Size: 2C-2Dh 0000h R/WO 16 bits
This value is used to identify the vendor of the subsystem.
Bit 15:0 Descriptions Subsystem Vendor ID (SUBVID)--R/WO. This field should be programmed during boot-up to indicate the vendor of the system board. After it has been written once, it becomes read only.
3.9.11
SID6--Subsystem Identification Register (Device 6)
Address Offset: Default Value: Access: Size: 2E-2Fh 0000h R/WO 16 bits
This value is used to identify a particular subsystem.
Bit 15:0 Descriptions Subsystem ID (SUBID)--R/WO. This field should be programmed during BIOS initialization. After it has been written once, it becomes read only.
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Register Description
3.10
Device 6 Memory-Mapped I/O Register Space
The DRAM timing and delay registers are located in the memory-mapped register (MMR) space of Device 6. Table 14 provides the register address map for this set of registers. Note: All accesses to these memory-mapped registers must be made as a single DWord (4 bytes) or less. Access must be aligned on a natural boundary.
Table 14. Device 6 Memory-Mapped I/O Register Address Map
Byte Address Offset 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008-000Bh 0010h 0011h 0012h 0013h 0014-005Fh 0060-0063h 0064-0067h 0068-006Bh 006C-FFFFh Register Symbol DRB0 DRB1 DRB2 DRB3 DRB4 DRB5 DRB6 DRB7 -- DRA0,1 DRA2,3 DRA4,5 DRA6,7 -- DRT -- DRC -- Register Name DRAM Row 0 Boundary DRAM Row 1 Boundary DRAM Row 2 Boundary DRAM Row 3 Boundary DRAM Row 4 Boundary DRAM Row 5 Boundary DRAM Row 6 Boundary DRAM Row 7 Boundary Intel Reserved DRAM Row 0,1 Attribute DRAM Row 2,3 Attribute DRAM Row 4,5 Attribute DRAM Row 6,7 Attribute Intel Reserved DRAM Timing Intel Reserved DRAM Controller Mode Intel Reserved Default Value 01h 01h 01h 01h 01h 01h 01h 01h -- 00h 00h 00h 00h -- 0000 0000h -- 0001 0001h -- Access RW RW RW RW RW RW RW RW -- RW RW RW RW -- RW -- RW --
3.10.1
DRB[0:7]--DRAM Row Boundary Register (Device 6, MMR)
Address Offset: Default Value: Access: Size: 0000h-0007h (DRB0-DRB7) 00h R/W 8 bits each register
The DRAM row Boundary registers define the upper boundary address of each DRAM row. Each row has its own single-byte DRB register. The granularity of these registers is 64 MB. For example, a value of 1 in DRB0 indicates that 64 MB of DRAM has been populated in the first row. When in either of the two dual-channel modes, the granularity of these registers is still 64 MB. In this case, the lowest order bit in each register is always programmed to 0 yielding a minimum granularity of 128 MB. Bit 7 of each of these registers is reserved and must be programmed to 0.
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Register Description
The remaining 7 bits of each of these registers are compared against address lines 31:26 to determine which row is being addressed by the current cycle. In either of the dual-channel modes, the GMCH supports a total of 4 rows of memory (only DRB0:3 are used). When in either of the dual-channel modes and four rows populated with 512-Mb technology, x8 devices, the largest memory size of 4 GB is supported. In this case, DRB3 is programmed to 40h. In the dual-channel modes, DRB[7:4] must be programmed to the same value as DRB3. In single-channel mode, all eight DRB registers are used. In this case, DRB[3:0] are used for the rows in channel A and DRB[7:4] are used for rows populated in channel B. If only channel A is populated, then only DRB[3:0] are used. DRB[7:4] are programmed to the same value as DBR3. If only channel B is populated, then DRB[7:4] are used and DRB[3:0] are programmed to 00h. When both channels are populated but not identically, all of the DRB registers are used. This configuration is referred to as "virtual single-channel mode." Row0: 0000h Row1: 0001h Row2: 0002h Row3: 0003h Row4: 0004h Row5: 0005h Row6: 0006h Row7: 0007h 0008h, reserved 0009h, reserved 000Ah, reserved 000Bh, reserved 000Ch, reserved 000Dh, reserved 000Eh, reserved 000Fh, reserved DRB0 = Total memory in Row0 (in 64-MB increments) DRB1 = Total memory in Row0 + Row1 (in 64-MB increments) DRB2 = Total memory in Row0 + Row1 + Row2 (in 64-MB increments) DRB3 = Total memory in Row0 + Row1 + Row2 + Row3 (in 64-MB increments) DRB4 = Total memory in Row0 + Row1 + Row2 + Row3 + Row4 (in 64-MB increments) DRB5 = Total memory in Row0 + Row1 + Row2 + Row3 + Row4 + Row5 (in 64-MB increments) DRB6 = Total memory in Row0 + Row1 + Row2 + Row3 + Row4 + Row5 + Row6 (in 64-MB increments) DRB7 = Total memory in Row0 + Row1 + Row2 + Row3 + Row4 + Row5 + Row6 + Row7 (in 64-MB increments) Each row is represented by a byte. Each byte has the following format:
Bit 7 Reserved. DRAM Row Boundary Address--R/W. This 7-bit value defines the upper and lower addresses for each SDRAM row. This 7-bit value is compared against address lines 0,31:26 (0 concatenated with the address bits 31:26) to determine which row the incoming address is directed. Default= 0000001b Description
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Register Description
3.10.2
DRA--DRAM Row Attribute Register (Device 6, MMR)
Address Offset: Default Value: Access: Size: 0010h-0013h 00h RO, R/W 8 bits each register
The DRAM Row Attribute registers define the page sizes to be used when accessing different rows or pairs of rows. The minimum page size of 4 KB occurs when in single-channel mode and either 128-Mb, x16 devices are populated or 256-Mb, x16 devices are populated. The maximum page size of 32 KB occurs when in dual-channel mode and 512-MB, x8 devices are populated. Each nibble of information in the DRA registers describes the page size of a row or pair of rows. When in either of the dual-channel modes, only registers 10h and 11h are used. The page size programmed reflects the page size for the pair of DIMMS installed. When in single-channel mode, registers 10h and 11h are used to specify page sizes for channel A and registers 12h and 13h are used to specify page sizes for channel B. If the associated row is not populated, the field must be left at the default value. Row0, 1:0010h Row2, 3:0011h Row4, 5:0012h Row6, 7:0013h
7 Rsvd 7 Rsvd 7 Rsvd 7 Rsvd 6 Row Attribute for Row 7 6 Row Attribute for Row 5 4 6 Row Attribute for Row 3 4 6 Row Attribute for Row 1 4 4 3 Rsvd 3 Rsvd 3 Rsvd 3 Rsvd 2 Row Attribute for Row 6 2 Row Attribute for Row 4 0 2 Row Attribute for Row 2 0 2 Row Attribute for Row 0 0 0
Bit 7 Reserved.
Description
Row Attribute for Odd-Numbered Row--R/W. This field defines the page size of the corresponding row. If the associated row is not populated, this field must be left at the default value. 6:4 000 = 4 KB 001 = 8 KB 010 = 16 KB 011 = 32 KB Others = Reserved Reserved. Row Attribute for Even-Numbered Row--R/W. This field defines the page size of the corresponding row. If the associated row is not populated, this field must be left at the default value. 2:0 000 = 4 KB 001 = 8 KB 010 = 16 KB 011 = 32 KB Others = Reserved
3
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Register Description
3.10.3
DRT--DRAM Timing Register (Device 6, MMR)
Address Offset: Default Value: Access: Size: 0060h-0063h 00000000h R/W 32 bits
This register controls the timing of micro-commands. When in virtual single-channel mode, the timing fields specified here apply even if two back-to-back cycles are to different physical channels. That is, the controller acts as if the two cycles are to the same physical channel.
Bit 31:11 Reserved Activate to Precharge Delay (tRAS) Max--R/W. These bits control the number of DRAM clocks for tRAS maximum. 10 0 = 120 s 1 = 70 s NOTE: DDR333 SDRAM require a shorter TRAS (max) of 70 s. Activate to Precharge delay (tRAS), Min--R/W. These bits control the number of DRAM clocks for tRAS minimum. 000 = 10 DRAM clocks 001 = 9 DRAM clocks 9:7 010 = 8 DRAM clocks 011 = 7 DRAM clocks 100 = 6 DRAM clocks 101 = 5 DRAM clocks others = Reserved CAS# Latency (tCL)--R/W. 00 = 2.5 DRAM clocks 6:5 01 = 2 DRAM clocks 10 = 3 DRAM clocks 11 = Reserved 4 Reserved DRAM RAS# to CAS# Delay (tRCD)--R/W. This bit controls the number of clocks inserted between an activate command and a read or write command to that bank. 3:2 00 = 4 DRAM clocks 01 = 3 DRAM clocks 10 = 2 DRAM clocks 11 = Reserved DRAM RAS# Precharge (tRP)--R/W. This bit controls the number of clocks that are inserted between a precharge command and an activate command to the same bank. 1:0 00 = 4 DRAM clocks (DDR 333) 01 = 3 DRAM clocks 10 = 2 DRAM clocks 11 = Reserved Description
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Register Description
3.10.4
DRC--DRAM Controller Mode Register (Device 6, MMR)
Address Offset: Default Value: Access: Size:
Bit 31:30 29 28:23 Reserved. Initialization Complete (IC)--R/W. This bit is used for communication of the software state between the memory controller and the BIOS. 1 = BIOS sets this bit to 1 after initialization of the DRAM memory array is complete. Reserved. Number of Channels (CHAN)--R/W. The GMCH memory controller supports three modes of operation. When programmed for single-channel mode, there are three options: channel A is populated, channel B is populated, or both are populated but not identically. When both channels have DIMMs installed and they are not identical (from channel to channel), the controller operates in a mode that is referred to as virtual single-channel. In this mode, the two physical channels are not in lock step but act as one logical channel. To operate in either dual-channel mode, the two channels must be populated identically. 00 = Single-channel or virtual single-channel 01 = Dual-channel, linear organization 10 = Dual-channel, tiled organization 11 = Reserved 20:11 Reserved Refresh Mode Select (RMS)--R/W. This field determines whether refresh is enabled and, if so, at what rate refreshes will be executed. 000 = Reserved 10:8 001 = Refresh enabled. Refresh interval 15.6 sec 010 = Refresh enabled. Refresh interval 7.8 sec 011 = Refresh enabled. Refresh interval 64 sec 111 = Refresh enabled. Refresh interval 64 clocks (fast refresh mode) Other = Reserved 7 Reserved.
0068h-006Bh 00000001h R/W, RO 32 bits
Description
22:21
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Register Description
Bit
Description Mode Select (SMS)--R/W. These bits select the special operational mode of the DRAM interface. The special modes are intended for initialization at power up. Note that FCSEN (fast CS#) must be set to 0 while SMS cycles are performed. It is expected that BIOS may program FCSEN to possible 1 only after initialization. 000 =Post Reset state - When the GMCH exits reset (power-up or otherwise), the mode select field is cleared to 000. During any reset sequence, while power is applied and reset is active, the GMCH de-asserts all CKE signals. After internal reset is de-asserted, CKE signals remain de-asserted until this field is written to a value different than 000. On this event, all CKE signals are asserted. During suspend (S3, S4), GMCH internal signal triggers SDRAM controller to flush pending commands and enter all rows into Self-Refresh mode. As part of resume sequence, the GMCH will be reset - which clears this bit field to 000 and maintains CKE signals deasserted. After internal reset is de-asserted, CKE signals remain de-asserted until this field is written to a value different than 000. On this event, all CKE signals are asserted.
6:4
001 =NOP Command Enable - All processor cycles to DRAM result in a NOP command on the DRAM interface. 010 =All Banks Pre-charge Enable - All processor cycles to DRAM result in an "all banks precharge" command on the DRAM interface. 011 =Mode Register Set Enable - All processor cycles to DRAM result in a "mode register" set command on the SDRAM interface. Host address lines are mapped to SDRAM address lines in order to specify the command sent. Host address HA[13:3] are mapped to memory address SMA[5:1]. 100 =Extended Mode Register Set Enable - All processor cycles to SDRAM result in an "extended mode register set" command on the SDRAM interface. Host address lines are mapped to SDRAM address lines in order to specify the command sent. Host address lines are mapped to SDRAM address lines in order to specify the command sent. Host address HA[13:3] are mapped to memory address SMA[5:1]. 101 =Reserved 110 =CBR Refresh Enable - In this mode all processor cycles to SDRAM result in a CBR cycle on the SDRAM interface 111 =Normal operation
3:2
Reserved DRAM Type (DT)--RO. This field is used to select between supported SDRAM types. 00 = Reserved 01 = Dual Data Rate SDRAM Other = Reserved.
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Register Description
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System Address Map
System Address Map
4
The processor in an 865G chipset system supports 4 GB of addressable memory space and 64 KB+3 of addressable I/O space. There is a programmable memory address space under the 1-MB region that is divided into regions that can be individually controlled with programmable attributes (e.g., disable, read/write, write only, or read only). Attribute programming is described in Chapter 3. This section focuses on how the memory space is partitioned and the use of the separate memory regions. The Pentium 4 processor family supports addressing of memory ranges larger than 4 GB. The GMCH claims any processor access over 4 GB and terminates the transaction without forwarding it to the hub interface or AGP (discarding the data terminates writes). For reads, the GMCH returns all zeros on the host bus. Note that the 865G chipset platform does not support the PCI Dual Address Cycle Mechanism; therefore, it does not allow addressing of greater than 4 GB on either the hub interface or AGP interface. In the following sections, it is assumed that all of the compatibility memory ranges reside on the hub interface/PCI. The exception to this rule is VGA ranges that may be mapped to AGP or to the IGD. In the absence of more specific references, cycle descriptions referencing PCI should be interpreted as the hub interface/PCI, while cycle descriptions referencing AGP are related to the AGP bus. The 865G chipset memory map includes a number of programmable ranges. Note: All of these ranges must be unique and non-overlapping. There are no hardware interlocks to prevent problems in the case of overlapping ranges. Accesses to overlapped ranges may produce indeterminate results.
4.1
System Memory Address Ranges
The GMCH provides a maximum system memory address decode space of 4 GB. The GMCH does not remap APIC memory space. The GMCH does not limit system memory space in hardware. It is the BIOS or system designers responsibility to limit memory population so that adequate PCI, AGP, High BIOS, and APIC memory space can be allocated. Figure 9 provides a simplified system memory address map. Figure 10 provides additional details on mapping specific memory regions as defined and supported by the GMCH.
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System Address Map
Figure 9. Memory System Address Map
4 GB PCI Memory Address Range
Graphics Memory
AGP Graphics Address (AGP) Range Aperture
Top of the DRAM Memory Main Memory Address Range 0
Independently Programmable Non-Overlapping Memory Windows
Figure 10. Detailed Memory System Address Map
FLASH APIC Reserved 4 GB Max Top of the Main Memory
PCI Memory Range*
*Contains AGP Window, GFX Apeture, PCI and ICH ranges 0FFFFFh TOP of DRAM Intel Reserved TOUD(OS Visible Main Memory) 0E0000h 0DFFFFh 16 MB Optional ISA Hole 15 MB Expansion Card BIOS and Buffer Area (128 KB; 16 KB x 8) 0C0000h 0BFFFFh Optionally mapped to the internal AGP 768 KB 0F0000h 0EFFFFh Lower BIOS Area (64 KB; 16 KB x 4) 896 KB Upper BIOS Area (64 KB) 960 KB 1 MB
DRAM Range
1 MB
DOS Compatibility Memory
640 KB
0A0000h 09FFFFh
Std PCI/ISA Video Mem (SMM Mem) 128 KB DOS Area (640 KB)
640 KB
0 MB
000000h
0 KB
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System Address Map
4.2
Compatibility Area
This area is divided into the following address regions:
* * * * *
0-640 KB MS-DOS Area. 640-768 KB Video Buffer Area. 768-896 KB in 16-KB sections (total of 8 sections) - Expansion Area. 896-960 KB in 16-KB sections (total of 4 sections) - Extended System BIOS Area. 960 KB-1 MB Memory (BIOS Area) - System BIOS Area.
There are fifteen memory segments in the compatibility area (see Table 15). Thirteen of the memory ranges can be enabled or disabled independently for both read and write cycles. Table 15. Memory Segments and Their Attributes
Memory Segments 000000h-09FFFFh 0A0000h-0BFFFFh 0C0000h-0C3FFFh 0C4000h-0C7FFFh 0C8000h-0CBFFFh 0CC000h-0CFFFFh 0D0000h-0D3FFFh 0D4000h-0D7FFFh 0D8000h-0DBFFFh 0DC000h-0DFFFFh 0E0000h-0E3FFFh 0E4000h-0E7FFFh 0E8000h-0EBFFFh 0EC000h-0EFFFFh 0F0000h-0FFFFFh Attributes Fixed: always mapped to main SDRAM Mapped to hub interface, AGP, or IGD: configurable as SMM space WE RE WE RE WE RE WE RE WE RE WE RE WE RE WE RE WE RE WE RE WE RE WE RE WE RE Comments 0 to 640 KB - DOS Region Video Buffer (physical SDRAM configurable as SMM space) Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS BIOS Extension BIOS Extension BIOS Extension BIOS Extension BIOS Area
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System Address Map
DOS Area (00000h-9FFFFh)
The DOS area is 640 KB in size and is always mapped to the main memory controlled by the GMCH.
Legacy VGA Ranges (A0000h-BFFFFh)
The legacy 128-KB VGA memory range A0000h-BFFFFh (Frame Buffer) can be mapped to IGD (Device 2), to AGP/PCI_B (Device 1), and/or to the hub interface depending on the programming of the VGA steering bits. Priority for VGA mapping is constant in that the GMCH always decodes internally mapped devices first. Internal to the GMCH, decode precedence is always given to IGD. The GMCH always positively decodes internally mapped devices, namely the IGD and AGP/ PCI_B. Subsequent decoding of regions mapped to AGP/PCI_B or the hub interface depends on the Legacy VGA configurations bits (VGA Enable and MDAP). This region is also the default for SMM space.
Compatible SMRAM Address Range (A0000h-BFFFFh)
When compatible SMM space is enabled, SMM-mode processor accesses to this range are routed to physical system SDRAM at this address. Non-SMM-mode processor accesses to this range are considered to be to the video buffer area as described above. AGP and HI originated cycles to enabled SMM space are not allowed and are considered to be to the video buffer area.
Monochrome Adapter (MDA) Range (B0000h-B7FFFh)
Legacy support requires the ability to have a second graphics controller (monochrome) in the system. Accesses in the standard VGA range are forwarded to IGD, AGP/PCI_B, and the hub interface (depending on configuration bits). Since the monochrome adapter may be mapped to anyone of these devices, the GMCH must decode cycles in the MDA range and forward them either to IGD, AGP/PCI_B, or to the hub interface. This capability is controlled by VGA steering bits and the legacy configuration bit (MDAP bit). In addition to the memory range B0000h to B7FFFh, the GMCH decodes I/O cycles at 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, and 3BFh and forwards them to the either the IGD, AGP/PCI_B, and/or the hub interface.
Expansion Area (C0000h-DFFFFh)
This 128-KB ISA Expansion region is divided into eight, 16-KB segments. Each segment can be assigned one of four read/write states: read-only, write-only, read/write, or disabled. Typically, these blocks are mapped through GMCH and are subtractively decoded to ISA space. Memory that is disabled is not remapped.
Extended System BIOS Area (E0000h-EFFFFh)
This 64-KB area is divided into four, 16-KB segments. Each segment can be assigned independent read and write attributes so it can be mapped either to main system memory or to hub interface. Typically, this area is used for RAM or ROM. Memory segments that are disabled are not remapped elsewhere.
System BIOS Area (F0000h-FFFFFh)
This area is a single, 64-KB segment. This segment can be assigned read and write attributes. It is by default (after reset) read/write disabled and cycles are forwarded to the hub interface. By manipulating the read/write attributes, the GMCH can "shadow" BIOS into the main system memory. When disabled, this segment is not remapped.
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4.3
Extended Memory Area
This memory area covers the 1 MB to 4 GB-1 (100000h-FFFFFFFFh) address range and is divided into the following regions:
* Main system SDRAM memory from 1 MB to the Top of Memory; maximum of 4-GB
SDRAM.
* AGP or PCI Memory space from the Top of Memory to 4 GB, with two specific ranges:
-- APIC Configuration Space from FEC0_0000h (4 GB-20 MB) to FECF_FFFFh and FEE0_0000h to FEEF_FFFFh -- High BIOS area from 4 GB to 4 GB - 2 MB
Main System Memory Address Range (0010_0000h to Top of Main Memory)
The address range from 1 MB to the top of system memory is mapped to system memory address range controlled by the GMCH. The Top of Main Memory (TOMM) is limited to 4-GB SDRAM. All accesses to addresses within this range will be forwarded by the GMCH to system memory unless a hole in this range is created using the fixed hole as controlled by the FDHC register. Accesses within this hole are forwarded to the hub interface. The GMCH provides a maximum system memory address decode space of 4 GB. The GMCH does not remap APIC memory space. The GMCH does not limit system memory address space in hardware.
4.3.1
15 MB-16 MB Window
A hole can be created at 15 MB-16 MB as controlled by the fixed hole enable (FDHC register) in Device 0 space. Accesses within this hole are forwarded to the hub interface. The range of physical SDRAM memory disabled by opening the hole is not remapped to the Top of the memory - that physical SDRAM space is not accessible. This 15-MB-16-MB hole is an optionally enabled ISA hole. Video accelerators originally used this hole. There is no inherent BIOS request for the 15-MB-16-MB hole.
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System Address Map
4.3.2
Pre-Allocated Memory
Voids of physical addresses that are not accessible as general system memory and reside within the system memory address range (< TOSM) are created for SMM-mode and legacy VGA graphics compatibility. For VGA graphics compatibility, pre-allocated memory is only required in non-local memory configurations. It is the responsibility of BIOS to properly initialize these regions. Table 16 details the location and attributes of the regions. Enabling/Disabling these ranges are described in the GMCH Control (GC) Register in Device 0.
Table 16. Pre-Allocated Memory
Memory Segments 00000000h-03E7FFFFh 03E80000h-03EFFFFFh 03E80000h-03EFFFFFh 03F00000h- 03FFFFFFh R/W SMM Mode Only - processor Reads SMM Mode Only - processor Reads R/W Attributes Comments Available System Memory 62.5 MB TSEG Address Range TSEG Pre-allocated Memory Pre-allocated Graphics VGA memory. 1 MB (or 512 K or 8 MB) when IGD is enabled.
Extended SMRAM Address Range (HSEG and TSEG)
The HSEG and TSEG SMM transaction address spaces reside in this extended memory area.
HSEG
SMM-mode processor accesses to enabled HSEG are remapped to 000A0000h-000BFFFFh. NonSMM-mode processor accesses to enabled HSEG are considered invalid and are terminated immediately on the FSB. The exceptions to this rule are Non-SMM-mode write back cycles that are remapped to SMM space to maintain cache coherency. AGP and HI originated cycles to enabled SMM space are not allowed. Physical SDRAM behind the HSEG transaction address is not remapped and is not accessible.
TSEG
TSEG can be up to 1 MB in size and is the first block after the top of usable physical memory. SMM-mode processor accesses to enabled TSEG access the physical SDRAM at the same address. Non-SMM-mode processor accesses to enabled TSEG are considered invalid and are terminated immediately on the FSB. The exceptions to this rule are Non-SMM-mode write back cycles that are directed to the physical SMM space to maintain cache coherency. AGP and HI originated cycles to enabled SMM space are not allowed. The size of the SMRAM space is determined by the USMM value in the SMRAM register. When the extended SMRAM space is enabled, non-SMM processor accesses and all other accesses in this range are forwarded to the hub interface. When SMM is enabled, the amount of memory available to the system is equal to the amount of physical SDRAM minus the value in the TSEG register.
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System Address Map
PCI Memory Address Range (Top of Main Memory to 4 GB)
The address range from the top of main SDRAM to 4 GB (top of physical memory space supported by the GMCH) is normally mapped via the hub interface to PCI. As a memory controller hub, there is one exception to this rule.
* Addresses decoded to MMIO for DRAM RCOMP configuration registers.
As an internal graphics configuration, there are two exceptions to this rule. Both of these exception cases are forwarded to the IGD.
* Addresses decoded to graphics configuration registers. * Addresses decoded to the memory-mapped range of the Internal Graphics Device (IGD).
As an AGP configuration, there are two exceptions to this rule.
* Addresses decoded to the AGP memory window defined by the MBASE, MLIMIT, PMBASE, *
Caution: and PMLIMIT registers are mapped to AGP. Addresses decoded to the graphics aperture range defined by the APBASE and APSIZE registers are mapped to the main SDRAM.
There are two sub-ranges within the PCI memory address range defined as APIC configuration space and High BIOS address range. As an Internal Graphics Device, the memory-mapped range of the Internal Graphics Device Must Not overlap with these two ranges. Similarly, as an AGP device, the AGP memory window and graphics aperture window Must Not overlap with these two ranges. These ranges are described in detail in the following paragraphs.
APIC Configuration Space (FEC0_0000h-FECF_FFFFh, FEE0_0000h- FEEF_FFFFh)
This range is reserved for APIC configuration space that includes the default I/O APIC configuration space. The default Local APIC configuration space is FEE0_0000h to FEEF_0FFFh. Processor accesses to the Local APIC configuration space do not result in external bus activity since the Local APIC configuration space is internal to the processor. However, an MTRR must be programmed to make the Local APIC range uncacheable (UC). The Local APIC base address in each processor should be relocated to the FEC0_0000h (4 GB-20 MB) to FECF_FFFFh range so that one MTRR can be programmed to 64 KB for the Local and I/O APICs. The I/O APIC(s) usually reside in the ICH5 portion of the chipset or as a stand-alone component. I/O APIC units will be located beginning at the default address FEC0_0000h. The first I/O APIC is located at FEC0_0000h. Each I/O APIC unit is located at FEC0_x000h where x is the I/O APIC unit number 0 through F(hex). This address range will be normally mapped to the hub interface. Note: There is no provision to support an I/O APIC device on AGP. The address range between the APIC configuration space and the High BIOS (FED0_0000h to FFDF_FFFFh) is always mapped to the hub interface.
High BIOS Area (FFE0_0000h-FFFF_FFFFh)
The top 2 MB of the Extended Memory Region is reserved for System BIOS (High BIOS), extended BIOS for PCI devices, and the A20 alias of the system BIOS. The processor begins execution from the High BIOS after reset. This region is mapped to the hub interface so that the upper subset of this region aliases to 16-MB-256-KB range. The actual address space required for the BIOS is less than 2 MB but the minimum processor MTRR range for this region is 2 MB so that the full 2 MB must be considered.
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System Address Map
4.4
AGP Memory Address Ranges
The GMCH can be programmed to direct memory accesses to the AGP bus interface when addresses are within either of two ranges specified via registers in GMCH's Device 1 configuration space. The first range is controlled via the Memory Base (MBASE) and Memory Limit (MLIMIT) registers. The second range is controlled via the Prefetchable Memory Base (PMBASE) and Prefetchable Memory Limit (PMLIMIT) registers. Conceptually, address decoding for each range follows the same basic concept. The top 12 bits of the respective Memory Base and Memory Limit registers correspond to address bits A[31:20] of a memory address. For the purpose of address decoding, the GMCH assumes that address bits A[19:0] of the memory base are zero and that address bits A[19:0] of the memory limit address are FFFFFh. This forces each memory address range to be aligned to 1-MB boundary and to have a size granularity of 1 MB. The GMCH positively decodes memory accesses to AGP memory address space as defined by the following equations:
Memory_Base_Address Address Memory_Limit_Address Prefetchable_Memory_Base_Address Address Prefetchable_Memory_Limit_Address
The window size is programmed by the plug-and-play configuration software. The window size depends on the size of memory claimed by the AGP device. Normally, these ranges reside above the top of main memory and below High BIOS and APIC address ranges. They normally reside above the top of memory (TOUD) so they do not steal any physical SDRAM memory space. It is essential to support a separate Prefetchable range in order to apply the USWC attribute (from the processor point of view) to that range. The USWC attribute is used by the processor for write combining. Note that the GMCH Device 1 memory range registers described above are used to allocate memory address space for any devices on AGP that require such a window. These devices include the AGP device, PCI-66 MHz/1.5 V agents, and multifunctional AGP devices where one or more functions are implemented as PCI devices. The PCICMD1 register can override the routing of memory accesses to AGP. In other words, the memory access enable bit must be set in the device 1 PCICMD1 register to enable the memory base/limit and prefetchable base/limit windows.
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Functional Description
Functional Description
5
This chapter describes the GMCH interfaces and functional units including the processor system bus interface, the AGP interface, system memory controller, integrated graphics device, DVO interfaces, display interfaces, power management, and clocking.
5.1
Processor Front Side Bus (FSB)
The GMCH supports a single Pentium 4 processor with 512-KB L2 cache on 0.13 micron process in a 478-pin package or the Pentium 4 processor on 90 nm process. The GMCH supports FSB frequencies of 400 MHz, 533 MHz, and 800 MHz using a scalable FSB VTT voltage and on-die termination. It supports 32-bit host addressing, decoding up to 4 GB of the processor's memory address space. Host-initiated I/O cycles are decoded to AGP/PCI_B, Hub Interface, or the GMCH configuration space. Host-initiated memory cycles are decoded to AGP/PCI_B, Hub Interface or system memory. All memory accesses from the host interface that hit the graphics aperture are translated using an AGP address translation table. AGP/PCI_B device accesses to non-cacheable system memory are not snooped on the host bus. Memory accesses initiated from AGP/PCI_B using PCI semantics and from the hub interface to system memory will be snooped on the host bus. The GMCH supports the Pentium 4 processor subset of the Enhanced Mode Scalable Bus. The cache line size is 64 bytes. Source synchronous transfer is used for the address and data signals. At 100/133/200 MHz bus clock the address signals are double pumped to run at 200/266/400 MHz and a new address can be generated every other bus clock. At 100/133/200 MHz bus clock the data signals are quad pumped to run at 400/533/800 MHz and an entire 64-B cache line can be transferred in two bus clocks. The GMCH integrates AGTL+ termination resistors on die. The GMCH has an IOQ depth of 12. The GMCH supports one outstanding deferred transaction on the FSB.
5.1.1
FSB Dynamic Bus Inversion
The GMCH supports Dynamic Bus Inversion (DBI) when driving and when receiving data from the processor. DBI limits the number of data signals that are driven to a low voltage on each quad pumped data phase. This decreases the worst-case power consumption of the GMCH. DINV[3:0]# indicate if the corresponding 16 bits of data are inverted on the bus for each quad pumped data phase: DINV[3:0]# DINV0# DINV1# DINV2# DINV3# Data Bits HD[15:0]# HD[31:16]# HD[47:32]# HD[63:48]#
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Functional Description
When the processor or the GMCH drives data, each 16-bit segment is analyzed. If more than 8 of the 16 signals would normally be driven low on the bus, the corresponding DINVx# signal will be asserted and the data will be inverted prior to being driven on the bus. When the processor or the GMCH receives data, it monitors DINV[3:0]# to determine if the corresponding data segment should be inverted.
5.1.2
FSB Interrupt Overview
Pentium 4 processors support FSB interrupt delivery. They do not support the APIC serial bus interrupt delivery mechanism. Interrupt related messages are encoded on the FSB as "Interrupt Message Transactions." In the 865G chipset platform FSB interrupts may originate from the processor on the system bus, or from a downstream device on the hub interface, or AGP. In the later case the GMCH drives the "Interrupt Message Transaction" onto the system bus. In the 865G chipset environment the ICH5 contains IOxAPICs, and its interrupts are generated as upstream HI memory writes. Furthermore, PCI 2.3 defines MSIs (Message Signaled Interrupts) that are also in the form of memory writes. A PCI 2.3 device may generate an interrupt as an MSI cycle on its PCI bus instead of asserting a hardware signal to the IOxAPIC. The MSI may be directed to the IOxAPIC which in turn generates an interrupt as an upstream hub interface memory write. Alternatively, the MSI may be directed directly to the FSB. The target of an MSI is dependent on the address of the interrupt memory write. The GMCH forwards inbound HI and AGP/PCI (PCI semantic only) memory writes to address 0FEEx_xxxxh to the FSB as "Interrupt Message Transactions."
5.1.2.1
Upstream Interrupt Messages
The GMCH accepts message-based interrupts from PCI (PCI semantics only) hub interface and forwards them to the FSB as Interrupt Message Transactions. The interrupt messages presented to the GMCH are in the form of memory writes to address 0FEEx_xxxxh. At the HI or PCI interface, the memory write interrupt message is treated like any other memory write; it is either posted into the inbound data buffer (if space is available) or retried (if data buffer space is not immediately available). Once posted, the memory write from PCI or hub interface to address 0FEEx_xxxxh is decoded as a cycle that needs to be propagated by the GMCH to the FSB as an Interrupt Message Transaction.
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5.2
System Memory Controller
The GMCH can be configured to support DDR266/333/400 MHz memory in single- or dualchannel mode. This includes support for:
* * * *
Up to 4 GB of 266/333/400 MHz DDR SDRAM DDR266, DDR333, and DDR400 unbuffered 184-pin DDR SDRAM DIMMs Up to 2 DIMMs per-channel, single-sided and/or double-sided Byte masking on writes through data masking.
Table 17. System Memory Capacity
DRAM Technology 128 Mb 256 Mb 512 Mb Smallest Increments 64 MB 128 MB 256 MB Largest Increments 256 MB 512 MB 1024 MB Maximum Capacity (4 DS DIMMs) 1024 MB 2048 MB 4096 MB
NOTE: The Smallest Increments column also represents the smallest possible single DIMM capacity.
DIMM population guidelines are shown in Figure 11 and Chapter 13. Figure 11. Single-Channel Mode Operation
No DIMMs CH A GMCH CH B No DIMMs SC Mode: CH A Only SC Mode: CH B Only VSC Mode: CH A and CH B GMCH CH B CH A GMCH CH B CH A
Figure 12. Dual-Channel Mode Operation
CH A GMCH CH B GMCH CH B CH A GMCH CH B CH A
No DIMMs
No DIMMs
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5.2.1
DRAM Technologies and Organization
Supported DRAM technologies and organizations include:
* All standard 128-Mb, 256-Mb and 512-Mb technologies and addressing are supported for x16
and x8 devices.
* All supported devices have 4 banks. * The GMCH supports page sizes. Page size is individually selected for every row
-- 4 KB, 8 KB, 16 KB for single-channel mode. -- 8 KB,16 KB, and 32 KB in dual-channel mode
* * * *
The DRAM sub-system supports a single or dual-channel, 64 b wide per channel There can be a maximum of four rows populated (two double-sided DIMMs) per channel. Mixed mode DDR DS-DIMMs (x8 and x16 on same DIMM) are not supported By using 512-Mb technology, the largest memory capacity is 2 GB per channel (64M x 8b x 8 devices x 4 rows = 2 GB) (8M x 16b x 4 devices x 1 rows = 64 MB)
* By using 128-Mb technology, the smallest memory capacity is 64 MB per channel
5.2.2
Memory Operating Modes
The GMCH supports the following modes of operation
* Single-channel mode (SC).
-- Populate channel A only -- Populate channel B Only -- Populate both channel A and B.
* Dual-channel lock step mode (DS).
-- DS linear mode. -- DS tiled mode. (internal graphics mode) The GMCH supports a special mode of addressing - Dynamic Addressing mode. All the abovementioned modes can be enabled with/without Dynamic addressing mode enabled. Table 18 summarizes the different operating modes GMCH memory controller can operate. Table 18. GMCH Memory Controller Operating Modes
Mode Type Channel A Only SC Mode Channel B Only Both Channel A and B DS Mode Linear Tiled Dynamic Addressing Mode Yes(1) Yes
(1)
Non-Dynamic Addressing Mode Yes Yes Yes Yes(1) Yes(1)
Yes(1) Yes Yes
NOTE: 1. Special cases - need to meet few requirements discussed in Section 5.2.2.1.
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5.2.2.1
Dynamic Addressing Mode
When the GMCH is configured to operate in this mode, FSB-to-memory bus address mapping undergoes a significant change compared to that of in a Linear Operating mode (normal operating mode). In non-dynamic mode, the row selection (row indicates the side of a DIMM) via chip select signals is accomplished based on the size of the row. For example, for a 512-Mb, 16Mx8x4b has a row size of 512 MB selected by CS0# and only four open pages can be maintained for the full 512 MB. This lowers the memory performance (increases read latencies) if most of the memory cycles are targeted to that single row, resulting in opening and closing of accessed pages in that row. Dynamic Addressing mode minimizes the overhead of opening/closing pages in memory banks allowing for row switching to be done less often.
5.2.3
Single-Channel (SC) Mode
If either only channel A or only channel B is populated, the GMCH is set to operate in singlechannel mode. Data is accessed in chunks of 64 bits (8 B) from the memory channels. If both channels are populated with uneven memory (DIMMs), the GMCH defaults to virtual singlechannel (VSC) mode. Even with similar memory configuration on both the channels, it is possible to force the GMCH to operate in single-channel mode, which by default is configured as Lock Step mode. The GMCH behaves identical in both single-channel and virtual single-channel modes (hereafter referred to as single-channel (SC) mode). In this mode of operation, the populated DIMMs configuration can be identical or completely different. In addition, for SC mode, not all the slots need to be populated. For example, populating only one DIMM in channel A is a valid configuration for SC mode. Likewise, in VSC mode odd number of slots can be populated. For Dynamic Mode operation, the requirement is to have an even number of rows (side of the DIMM) populated. In SC, dynamic mode operation can be enabled with one single-sided (SS), two SS or two double-sided (DS). For VSC mode, both the channels need to have an identical row structure.
5.2.3.1 5.2.3.2
Linear Mode
This mode is the normal mode of operation for the GMCH with internal graphics device disabled.
Tiled Mode
This mode was specifically aimed at improving the performance of the Integrated Graphics Device.
5.2.4
Memory Address Translation and Decoding
The address translation and decoding for the GMCH is provided in Table 19 through Table 24. The supported DIMM configurations are listed in the following bullets. Refer to Section 5.2.5 for details about the configurations being double-sided versus single-sided.
* * * * * *
Note:
Technology 128 Mbit - 16Mx8 - page size of 8 KB - row size of 128 MB Technology 128 Mbit - 8Mx16 - page size of 4 KB - row size of 64 MB Technology 256 Mbit - 32Mx8 - page size of 8 KB - row size of 256 MB Technology 256 Mbit - 16Mx16 - page size of 4 KB - row size of 128 MB Technology 512 Mbit - 32Mx16 - page size of 8 KB - row size of 256 MB Technology 512 Mbit - 64Mx8 - page size of 16 KB - row size of 512 MB
In Table 19 through Table 24 A0, A1, ... refers to memory address MA0, MA1, .... The table cell contents refers to host address signals HAx.
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Table 19. DRAM Address Translation (Single-Channel Mode) (Non-Dynamic Mode)
Tech. Config. Row size Page size 64MB 4KB 128MB 8KB Row / Column Addr BA1 BA0 A12 A11 A10 A9 / Bank Row Col Row Col 26 25 13 13 14 14 12 12 13 13 16 16 15 AP 15 AP 26 12 14 A8 A7 A6 A5 A4 A3 A2 A1 A0
128Mb 8Mx16
12x9x2
25 11 25 11
24 10 24 10
23 9 23 9
22 8 22 8
21 7 21 7
20 6 20 6
19 5 19 5
18 4 18 4
17 3 17 3
128Mb 16Mx8
12x10x2
256Mb 16Mx16
128MB 4KB 256MB 8KB
13x9x2
Row Col Row Col
26
13 13
12 12 13 13
26
16
15 AP
14
25 11
24 10 24 10
23 9 23 9
22 8 22 8
21 7 21 7
20 6 20 6
19 5 19 5
18 4 18 4
17 3 17 3
256Mb 32Mx8
13x10x2
27
14 14
27
16
15 AP
26 12
25 11
512Mb 32Mx16
256MB 8KB 512MB 16KB
13x10x2
Row Col Row Col
27
14 14
13 13 14 14
27
16
15 AP
26 12 26 12
25 11 25 11
24 10 24 10
23 9 23 9
22 8 22 8
21 7 21 7
20 6 20 6
19 5 19 5
18 4 18 4
17 3 17 3
512Mb 64Mx8
13x11x2
28
15 15
28
16 13
27 AP
Table 20. DRAM Address Translation (Dual-Channel Mode, Discrete) (Non-Dynamic Mode)
Row size Tech. Config. Page size 128Mb 8Mx16 64MB 4KB 128MB 8KB Row / Column Addr BA1 BA0 A12 A11 A10 A9 / Bank Row Col Row Col 26 25 14 14 14 14 13 13 15 15 16 16 15 AP 27 AP 26 13 26 A8 A7 A6 A5 A4 A3 A2 A1 A0
12x9x2
25 12 25 12
24 11 24 11
23 10 23 10
22 9 22 9
21 8 21 8
20 7 20 7
19 6 19 6
18 5 18 5
17 4 17 4
128Mb 16Mx8
12x10x2
256Mb 16Mx16
128MB 4KB 256MB 8KB
13x9x2
Row Col Row Col
26
14 14
13 13 15 15
27
16
15 AP
26
25 12
24 11 24 11
23 10 23 10
22 9 22 9
21 8 21 8
20 7 20 7
19 6 19 6
18 5 18 5
17 4 17 4
256Mb 32Mx8
13x10x2
27
14 14
28
16
27 AP
26 13
25 12
512Mb 32Mx16
256MB 8KB 512MB 16KB
13x10x2
Row Col Row Col
27
14 14
15 15 15 15
28
16
27 AP
26 13 26 13
25 12 25 12
24 11 24 11
23 10 23 10
22 9 22 9
21 8 21 8
20 7 20 7
19 6 19 6
18 5 18 5
17 4 17 4
512Mb 64Mx8
13x11x2
28
16 16
28
29 14
27 AP
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Table 21. DRAM Address Translation (Dual-Channel Mode, Internal Gfx) (Non-Dynamic Mode)
Tech. Config. Row size Row / Column Addr BA1 BA0 A12 A11 A10 A9 Page / Bank size 64MB 4KB 128MB 8KB 12x9x2 Row Col Row Col 26 25 14 14 14 14 13 13 15 15 16 16 15 AP 27 AP 26 13 26 A8 A7 A6 A5 A4 A3 A2 A1 A0
128Mb 8Mx16
25 12 25 12
24 11 24 11
23 10 23 10
22 9 22 9
21 8 21 8
20 7 20 7
19 6 19 6
18 5 18 5
17 3 17 3
128Mb 16Mx8
12x10x2
256Mb 16Mx16
128MB 4KB 256MB 8KB
13x9x2
Row Col Row Col
26
14 14
13 13 15 15
27
16
15 AP
26
25 12
24 11 24 11
23 10 23 10
22 9 22 9
21 8 21 8
20 7 20 7
19 6 19 6
18 5 18 5
17 3 17 3
256Mb 32Mx8
13x10x2
27
14 14
28
16
27 AP
26 13
25 12
512Mb 32Mx16
256MB 8KB 512MB 16KB
13x10x2
Row Col Row Col
27
14 14
15 15 15 15
28
16
27 AP
26 13 26 13
25 12 25 12
24 11 24 11
23 10 23 10
22 9 22 9
21 8 21 8
20 7 20 7
19 6 19 6
18 5 18 5
17 3 17 3
512Mb 64Mx8
13x11x2
28
16 16
28
29 14
27 AP
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Table 22. DRAM Address Translation (Single-Channel Mode) (Dynamic Mode)
Tech. Config. Row size Row / Column Addr BA1 BA0 A12 A11 A10 A9 Page / Bank size 64MB 4KB 128MB 8KB 12x9x2 Row Col Row Col 26 25 12 12 18 18 18 18 13 13 16 16 13 AP 14 AP 26 12 14 A8 A7 A6 A5 A4 A3 A2 A1 A0
128Mb 8Mx16
27 11 28 11
26 10 27 10
23 9 23 9
22 8 22 8
21 7 21 7
25 6 25 6
24 5 24 5
15 4 15 4
17 3 17 3
128Mb 16Mx8
12x10x2
256Mb 16Mx16
128MB 4KB 256MB 8KB
13x9x2
Row Col Row Col
26
12 12
18 18 13 13
26
16
13 AP
14
28 11
27 10 24 10
23 9 23 9
22 8 22 8
21 7 21 7
25 6 29 6
24 5 28 5
15 4 15 4
17 3 17 3
256Mb 32Mx8
13x10x2
27
18 18
27
16
14 AP
26 12
25 11
512Mb 32Mx16
256MB 8KB 512MB 16KB
13x10x2
Row Col Row Col
27
18 18
13 13 18 18
27
16
14 AP
26 12 26 12
25 11 25 11
24 10 24 10
23 9 23 9
22 8 22 8
21 7 21 7
29 6 30 6
28 5 29 5
15 4 15 4
17 3 17 3
512Mb 64Mx8
13x11x2
28
14 14
28
16 13
27 AP
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Table 23. DRAM Address Translation (Dual-Channel Mode, Discrete) (Dynamic Mode)
Tech. Config. Row size Row / Column Addr BA1 BA0 A12 A11 A10 A9 Page / Bank size 64MB 4KB 128MB 8KB 12x9x2 Row Col Row Col 26 25 18 18 14 14 13 13 18 18 16 16 14 AP 27 AP 26 13 26 A8 A7 A6 A5 A4 A3 A2 A1 A0
128Mb 8Mx16
28 12 25 12
27 11 24 11
23 10 23 10
22 9 22 9
21 8 21 8
25 7 29 7
24 6 28 6
15 5 15 5
17 4 17 4
128Mb 16Mx8
12x10x2
256Mb 16Mx16
128MB 4KB 256MB 8KB
13x9x2
Row Col Row Col
26
18 18
13 13 18 18
27
16
14 AP
26
25 12
24 11 24 11
23 10 23 10
22 9 22 9
21 8 21 8
29 7 30 7
28 6 29 6
15 5 15 5
17 4 17 4
256Mb 32Mx8
13x10x2
27
14 14
28
16
27 AP
26 13
25 12
512Mb 32Mx16
256MB 8KB 512MB 16KB
13x10x2
Row Col Row Col
27
14 14
18 18 15 15
28
16
27 AP
26 13 26 13
25 12 31 12
24 11 30 11
23 10 23 10
22 9 22 9
21 8 21 8
30 7 25 7
29 6 24 6
15 5 15 5
17 4 17 4
512Mb 64Mx8
13x11x2
28
18 18
28
29 14
27 AP
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Table 24. RAM Address Translation (Dual-Channel Mode, Internal Gfx) (Dynamic Mode)
Tech. Config. Row size Row / Column Addr BA1 BA0 A12 A11 A10 A9 Page / Bank size 64MB 4KB 128MB 8KB 12x9x2 Row Col Row Col 26 25 18 18 14 14 13 13 18 18 16 16 14 AP 27 AP 26 13 26 A8 A7 A6 A5 A4 A3 A2 A1 A0
128Mb 8Mx16
28 12 25 12
27 11 24 11
23 10 23 10
22 9 22 9
21 8 21 8
25 7 29 7
24 6 28 6
15 5 15 5
17 3 17 3
128Mb 16Mx8
12x10x2
256Mb 16Mx16
128MB 4KB 256MB 8KB
13x9x2
Row Col Row Col
26
18 18
13 13 18 18
27
16
14 AP
26
25 12
24 11 24 11
23 10 23 10
22 9 22 9
21 8 21 8
29 7 30 7
28 6 29 6
15 5 15 5
17 3 17 3
256Mb 32Mx8
13x10x2
27
14 14
28
16
27 AP
26 13
25 12
512Mb 32Mx16
256MB 8KB 512MB 16KB
13x10x2
Row Col Row Col
27
14 14
18 18 15 15
28
16
27 AP
26 13 26 13
25 12 31 12
24 11 30 11
23 10 23 10
22 9 22 9
21 8 21 8
30 7 25 7
29 6 24 6
15 5 16 5
17 3 17 3
512Mb 64Mx8
13x11x2
28
18 18
28
29 14
27 AP
5.2.5
Memory Organization and Configuration
In the following discussion the term "row" refers to a set of memory devices that are simultaneously selected by a chip select signal. The GMCH supports a maximum of four rows of memory. For the purposes of this discussion, a "side" of a DIMM is equivalent to a "row" of SDRAM devices. The memory bank address lines and the address lines allow the GMCH to support 64-bit wide x8 and x16 DIMMs using 128-Mb, 256-Mb, and 512-Mb SDRAM technology. For the DDR SDRAM interface, Table 25 lists the supported configurations. Note that the GMCH supports configurations defined in the JEDEC DDR DIMM specification only (A, B, C). NonJEDEC standard DIMMs (e.g., double-sided x16 DDR SDRAM DIMMs) are not supported. For additional information on DIMM configurations, refer to the JEDEC DDR DIMM specification.
Table 25. Supported DDR DIMM Configurations
Density Device Width Single / Double 184 pin DDR DIMMs x8 SS/DS 128/256 MB 128 Mbit x16 SS/DS 64 MB/NA x8 SS/DS 256/512 MB 256 Mbit x16 SS/DS 128 MB/NA x8 SS/DS 512/1024 MB 512 Mbit x16 SS/DS 256 MB/NA
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5.2.6
Configuration Mechanism for DIMMS
Detection of the type of SDRAM installed on the DIMM is supported via the Serial Presence Detect (SPD) mechanism as defined in the JEDEC DIMM specification. This uses the SCL, SDA, and SA[2:0] pins on the DIMMs to detect the type and size of the installed DIMMs. No special programmable modes are provided on the GMCH for detecting the size and type of memory installed. Type and size detection must be accomplished via the serial presence detection pins and is required to configure the GMCH.
5.2.6.1
Memory Detection and Initialization
Before any cycles to the memory interface can be supported, the GMCH SDRAM registers must be initialized. The GMCH must be configured for operation with the installed memory types. Detection of memory type and size is accomplished via the System Management Bus (SMBus) interface on the ICH5. This two-wire bus is used to extract the SDRAM type and size information from the Serial Presence Detect port on the SDRAM DIMMs. SDRAM DIMMs contain a 5-pin Serial Presence Detect interface, including SCL (serial clock), SDA (serial data), and SA[2:0]. Devices on the SMBus bus have a 7-bit address. For the SDRAM DIMMs, the upper four bits are fixed at 1010. The lower three bits are strapped on the SA[2:0] pins. SCL and SDA are connected to the System Management Bus on the ICH5. Thus, data is read from the Serial Presence Detect port on the DIMMs via a series of I/O cycles to the ICH5. BIOS needs to determine the size and type of memory used for each of the rows of memory to properly configure the GMCH memory interface.
5.2.6.2
SMBus Configuration and Access of the Serial Presence Detect Ports
For more details, refer to the Intel(R) 82801EB I/O Controller Hub 5 (ICH5) and Intel(R) 82801ER I/O Controller Hub 5R (ICH5R) Datasheet.
5.2.6.3
Memory Register Programming
This section provides an overview of how the required information for programming the SDRAM registers is obtained from the Serial Presence Detect ports on the DIMMs. The Serial Presence Detect ports are used to determine Refresh Rate, SMA and SMD Buffer Strength, Row Type (on a row-by-row basis), SDRAM Timings, Row Sizes, and Row Page Sizes. Table 26 lists a subset of the data available through the on board Serial Presence Detect ROM on each DIMM.
Table 26. Data Bytes on DIMM Used for Programming DRAM Registers
Byte 2 3 4 5 11 12 17 Memory type (DDR SDRAM) Number of row addresses, not counting bank addresses number of column addresses Number of banks of SDRAM (single- or double-sided DIMM) ECC, non-ECC (865G chipset GMCH does not support ECC) Refresh rate Number of banks on each device Function
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Table 26 is only a subset of the defined SPD bytes on the DIMMs. These bytes collectively provide enough data for programming the GMCH SDRAM registers.
5.2.7
Memory Thermal Management
The GMCH provides a thermal management method that selectively reduces reads and writes to DRAM when the access rate crosses the allowed thermal threshold. Read and write thermal management operate independently, and have their own 64-bit register to control operation. Memory reads typically causes power dissipation in the DRAM chips while memory writes typically causes power dissipation in the GMCH.
5.2.7.1
Determining When to Thermal Manage
Thermal management may be enabled by one of two mechanisms:
* Software forcing throttling via the SRT (SWT) bit. * Counter Mechanism.
5.3
Accelerated Graphics Port (AGP)
The GMCH supports AGP 3.0 with limited AGP 2.0 compatibility. The electrical characteristics are supported for AGP 3.0 (0.8 V swing) and the AGP 2.0 (1.5 V swing). The GMCH may be operated in 1X and 4X for AGP 2.0 mode at 1.5 V; 3.3 V electrical characteristics are not supported. The GMCH has a 32 deep AGP request queue. The GMCH integrates two fully-associative 10 entry Translation Look-aside Buffer. This 20 entry buffer is used for both reads and writes. The GMCH multiplexes an AGP interface with two DVO ports. When an external AGP device is utilized, the multiplexed DVO ports are not available as the GMCH's IGD will be disabled. For more information on the multiplexed DVO interface, see Section 5.5.2. See the AGP Revision 3.0 specification for additional details about the AGP interface.
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5.3.1
GMCH AGP Support
Table 27. AGP Support Matrix
Parameter Data Rate Electricals AGP 3.0 4X or 8X 0.8 V swing, parallel terminated Most control signals active high Only low priority (renamed Async) Strobe First - Strobe Second Protocol Removed No Required Yes Required for AGP accesses outside of the aperture, and for FRAME-based accesses AGP 2.0 4X, or 1X 1.5 V swing serial terminated Most control signals active low High and low priority commands supported. Strobe - Strobe# protocol. Supported Yes No No Required only for FRAME-based accesses. SBA required for AGP 3.0 New to AGP 3.0. New to AGP 3.0 This change was necessary to eliminate current flow in the idle state. Parallel termination has a large current flow for a high level. High priority does not have a good usage model. Comments GMCH does not Support AGP 2X
Signal Polarity Hi / Low priority commands Strobe Protocol Long transactions PIPE# support Calibration Cycle Dynamic Bus Inversion Coherency
5.3.2
Selecting between AGP 3.0 and AGP 2.0
The GMCH supports both AGP 3.0 and limited AGP 2.0, allowing a "Universal AGP 3.0 motherboard" implementation. Whether AGP 2.0 or AGP 3.0 mode is used is determined by the graphics card installed. An AGP 2.0 card will put the system into AGP 2.0. An AGP 3.0 card will put the system into AGP 3.0 mode. The mode is selected during RESET by a hardware mechanism which is described in Section 5.3.3.1. The mode determines the electrical mode and can not be dynamically changed once the system powers up.
5.3.3
AGP 3.0 Downshift (4X Data Rate) Mode
AGP 3.0 supports both an 8X data rate and a 4X data rate. The purpose of the 4X data rate is to allow a fallback mode when board routing or other reasons make the 8X data rate marginal. Some AGP4X graphics cards currently fall back to a 2X data rate when board layout or other issues arise. This is referred as "downshift" mode. Since AGP 2X is not supported, any card falling back to 2X will be running in a non supported mode. When in AGP 3.0 mode in the 4X data rate, all of the AGP 3.0 protocols are used.
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Table 28. AGP 3.0 Downshift Mode Parameters
Parameter Data rate VREF level Signaling Polarity of GREQ, GGNT, GDEVSEL, GFRAME, GIRDT, GTRDY, GSTOP, RBF, WBF Polarity of SBA GCBE polarity Strobe definition DBI used? PIPE# allowed Commands supported Isoch supported Calibration cycles included AGP 2.0 Signaling (All Data Rates) 1X, 4X 0.75 V 2.0 (1.5 V) Active low normal (111 = idle) GC/BE# Strobe Strobe# No Yes AGP 2.0 commands No No AGP 3.0 Signaling (4X Data Rate) 4X 0.35 V 3.0 signaling (0.8 V swing) Active high inverted (000 = idle) GC#/BE StrobeFirst StrobeSecond Disabled on xmit No AGP 3.0 commands (Not supported) Yes AGP 3.0 Signaling (8X Data Rate) 8X 0.35 V 3.0 signaling (0.8 V swing) Active high inverted (000 = idle) GC#/BE StrobeFirst StrobeSecond Yes No AGP 3.0 commands No Yes
5.3.3.1
Mechanism for Detecting AGP 2.0, AGP 3.0, or Intel(R) DVO
Two new signals are provided in the AGP 3.0 specification to allow for detection of an AGP 3.0 capable graphics card by the motherboard and an AGP 3.0 capable motherboard by the graphics card respectively. The signals are:
* GC_DET#: Pulled low by an AGP 3.0 graphics card; left floating by an AGP 2.0 graphics
card.
* MB_DET#: Pulled low by an AGP 3.0 motherboard; left floating by an AGP 2.0 motherboard.
The 3.0 capable motherboard uses GC_DET# to determine whether to generate VREF of 0.75 V (floating GC_DET# for 2.0 graphics card), or 0.35 V (GC_DET# low) to the graphics card. This is sent to the graphics card via the VREFCG pin on the AGP connector. Similarly, the 3.0 capable graphics card uses MB_DET# to determine whether to generate VREF of 0.75 V (floating MB_DET# on 2.0 motherboard), or 0.35 V (MB_DET# low) to the motherboard. The card could also use this pin as a strap to determine 2.0 or 3.0 mode. Note, however, that VREFGC is not used by the GMCH. Instead, VREFCG is used to account for the DVO ADD card, where VREFGC is not connected. The GMCH detects whether the graphics card connected is AGP 2.0 or AGP 3.0 via the voltage level driven into the GVREF pin (0.35 V{< 0.55 V} = AGP 3.0; 0.75 V{>0.55 V} = AGP 2.0). GVREF is driven by VREFCG on the motherboard. An ADD card pulls the GPAR/ADD_DETECT# pin low and leaves GC_DET# pin unconnected. Since GC_DET# is unconnected, the VREF generator generates an AGP 2.0 compliant voltage, 0.75 V to the GVREF pin. This is detected by the VREF voltage comparator, which drives a "live" AGP 3.0 mode detect signal to GPAR (and other AGP I/O buffers), as well as the pull-up/pull-
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down controlling logic on the AGP I/O buffers, selecting the weak pull-up on GPAR. On the assertion of PWROK, a 0 is detected on the GPAR pin and is latched into the GMCHCFG.3 strap bit to select DVO over AGP. At the assertion of PWROK, the AGP 3.0 detect signal (value 0) is also latched into the AGPSTAT.3 strap bit. Note that a 0 in AGP 3.0 detect is meaningless when DVO is selected. An AGP 2.0 card tri-states GPAR and leaves the GC_DET# pin unconnected. GVREF = 0.75 V and GPAR is weakly pulled high during assertion of PWROK; a 1 is latched into GMCHCFG.3 strap bit to select AGP. AGP 3.0 detect value latched on the assertion of PWROK = 0 indicating AGP 2.0 mode. An AGP 3.0 card terminates GPAR low, and pulls GC_DET# low, causing the VREF generator to drive 0.35 V to GVREF. Note that during the assertion of PWROK, GPAR = 0 and AGP 3.0 detect = 1. To work correctly when AGP 3.0 detect = 1, AGP must be selected over DVO (i.e., when AGP 3.0 detect = 1, AGP/DVO# strap value must also be 1, regardless of the value on GPAR). Table 29. Pin and Strap Values Selecting Intel(R) DVO, AGP 2.0, and AGP 3.0
Card Plugged Into AGP Connector ADD card AGP 2.0 card AGP 3.0 card (1) Pull-up/ Termination on GPAR Pin Prior to Assertion of PWROK pull-up pull-up termination to ground GPAR/ ADD_DETECT# value on PWROK Assertion 0 1 0 AGP 3.0 Detect Value on PWROK Assertion 0 (0.75 V) 0 (0.75 V) 1 (0.35 V) GMCHCFG.3 Strap Bit (AGP/DVO#) 0 1 1 AGPSTAT.3 Strap Bit (AGP 3.0 Detect) 0 0 1
NOTE: 1. Difference between GPAR/ADD_DETECT# and GMCHCFG.3 value.
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5.3.4
AGP Target Operations
As an initiator, the GMCH does not initiate cycles using AGP enhanced protocols. The GMCH supports AGP target interface to main memory only. The GMCH supports interleaved AGP and PCI transactions. AGP 2.0 and AGP 3.0 support different command types, as indicated in Table 30.
Table 30. AGP 3.0 Commands Compared to AGP 2.0
GC/BE[3:0]# (GC#/BE[3:0]) Encoding 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 APG 2.0 Command Read (Low Priority) Read (High Priority) Reserved Reserved Write (Low Priority) Write (High Priority) Reserved Reserved Long Read (Low Priority) Long Read (High Priority) Flush (Low Priority) Reserved Fence (Low Priority) Reserved (was DAC cycle) Reserved Reserved AGP 3.0 Command Read (Asynchronous) Reserved Reserved ISOCH Read (NOT SUPPORTED) Write (Asynchronous) Reserved ISOCH Write, Unfenced (NOT SUPPORTED) ISOCH Write, Fenced (NOT SUPPORTED) Reserved Reserved Flush Reserved) Fence (for reads and writes) Reserved (was DAC cycle) Isoch Align (NOT SUPPORTED) Reserved
5.3.5
AGP Transaction Ordering
High priority reads and writes are not checked for conflicts between themselves or normal priority reads and writes. AGP commands (delivered via PIPE# or SBA, not FRAME#) snoop the global SDRAM write buffer.
Table 31. Supported Data Rates
Signaling Level Data Rate 0.8 V PCI-66 1X AGP 2X AGP 4X AGP 8X AGP Yes Yes No Yes Yes 1.5 V Yes Yes See Note Yes No 3.3 V No No No No No
NOTE: AGP 2X is not supported on the GMCH.
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5.3.6
Support for PCI-66 Devices
The GMCH's AGP interface may be used as a PCI-66 MHz interface with the following restrictions: 1. Support for 1.5 V operation only. 2. Support for only one device. The GMCH does not provide arbitration or electrical support for more than one PCI-66 device. 3. The PCI-66 device must meet the AGP 2.0 electrical specification. 4. The GMCH does not provide full PCI-to-PCI bridge support between AGP/PCI and hub interface. Traffic between AGP and hub interface is limited to hub interface-to-AGP memory writes. 5. LOCK# signal is not present. Neither inbound nor outbound locks are supported. 6. SERR# / PERR# signals are not present. 7. 16-clock Subsequent Data Latency timer (instead of 8).
5.3.7
8X AGP Protocol
The GMCH supports 1X and 4X AGP operation in 2.0 mode, and 4X and 8X in 3.0 mode. Bit 3 of the AGP status register is set to 0 in AGP 2.0 mode, and 1 in APG 3.0 mode. The GMCH indicates that it supports 8X data transfers in AGP 3.0 mode through RATE[1] of the AGP status register. When DATA_RATE[1] of the AGP Command Register is set to 1 during system initialization, the GMCH will perform AGP read and write data transactions using 8X protocol. This bit is set once during initialization and the data transfer rate cannot be changed dynamically. The 8X data transfer protocol provides 2.1 GB/s transfer rates. In 8X mode, 32 bytes of data are transferred during each 66 MHz clock period. The minimum throttleable block size remains four, 66 MHz clocks, which means 128 bytes of data is transferred per block.
5.3.7.1
Fast Writes
The Fast Write (FW) transaction is from the core logic to the AGP master acting as a PCI target. This type of access is required to pass data/control directly to the AGP master instead of placing the data into main memory and then having the AGP master read the data. For 1X transactions, the protocol simply follows the PCI bus specification. However, for higher speed transactions (4X or 8X), FW transactions follow a combination for PCI and AGP bus protocols for data movement. The GMCH only supports the AGP 1.5 V connector, which permits a 1.5 V AGP add-in card to be supported by the system.
5.3.7.2
PCI Semantic Transactions on AGP
The GMCH accepts and generates PCI semantic transactions on the AGP bus. The GMCH guarantees that PCI semantic accesses to SDRAM are kept coherent with the processor caches by generating snoops to the processor bus.
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5.4
Integrated Graphics Controller
The GMCH provides a highly integrated graphics accelerator and chipset while allowing a flexible integrated system graphics solution.
Figure 13. GMCH Graphics Block Diagram
Video Engine 2D Engine DAC Cntl Mux Port Alpha Blend / Gamma / CRC DVOB DVOC
VGA Overlay Cursor
Instr./ Data
3D Engine Setup/Transform Scan Conversion Texture Conversion Raster Engine
Primary Display
DDC
High bandwidth access to data is provided through the graphics and system memory ports. The GMCH can access graphics data located in system memory at 2.1 GB/s - 6.4 GB/s (depending on memory configuration). The GMCH uses Intel's Direct Memory Execution model to fetch textures from system memory. The GMCH includes a cache controller to avoid frequent memory fetches of recently used texture data. The GMCH is able to drive an integrated DAC, and/or two DVO ports (multiplexed with AGP) capable of driving an ADD card. The DAC is capable of driving a standard progressive scan analog monitor with resolutions up to 2048x1536 @ 75Hz. The DVO ports are capable of driving a variety of TV-Out, TMDS, and LVDS transmitters. As seen in Figure 13, the Internal Graphics Device contains several types of components. The major components in the IGD are the engines, planes, pipes and ports. The GMCH has a 3D/2D Instruction Processing unit to control the 3D and 2D engines. The IGD's 2D and 3D engines are fed with data through the memory controller. The output of the engines are surfaces sent to memory, which are then retrieved and processed by the GMCH's planes. The GMCH contains a variety of planes, such as display, overlay, cursor, and VGA. A plane consists of rectangular shaped image that has characteristics such as source, size, position, method, and format. These planes get attached to source surfaces, which are rectangular memory surfaces with a similar set of characteristics. They are also associated with a particular destination pipe. A pipe consists of a set of combined planes and a timing generator. The GMCH has a single display pipe, which means that the GMCH can only support a single display stream. A port is the destination for the result of the pipe. The GMCH contains three display ports, 1 analog (DAC), and two digital (DVO ports B and C). The ports will be explained in more detail in Section 5.5. The entire IGD is fed with data from its memory controller. The GMCH's graphics performance is directly related to the amount of bandwidth available. If the engines are not receiving data fast enough from the memory controller (e.g., single-channel DDR266), the rest of the IGD will also be affected.
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Functional Description
5.4.1
3D Engine
The 3D engine of the GMCH has been designed with a deep pipelined architecture, where performance is maximized by allowing each stage of the pipeline to simultaneously operate on different primitives or portions of the same primitive. The GMCH supports perspective-correct texture mapping, multitextures, bump-mapping, cubic environment maps, bilinear, trilinear and anisotropic MIP mapped filtering, Gouraud shading, alpha-blending, vertex and per pixel fog and Z/W buffering. The 3D pipeline subsystem performs the 3D rendering acceleration. The main blocks of the pipeline are the setup engine, scan converter, texture pipeline, and raster pipeline. A typical programming sequence would be to send instructions to set the state of the pipeline followed by rending instructions containing 3D primitive vertex data. The engines' performance is dependent on the memory bandwidth available. Systems that have more bandwidth available will significantly outperform systems with less bandwidth. The engines' performance is also dependent on the core clock frequency. The higher the frequency, the more data is processed.
5.4.1.1
Setup Engine
The setup stage of the pipeline takes the input data associated with each vertex of a 3D primitive and computes the various parameters required for scan conversion. In formatting this data, GMCH maintains sub-pixel accuracy.
3D Primitives and Data Formats Support
The 3D primitives rendered by GMCH are points, lines, discrete triangles, line strips, triangle strips, triangle fans and polygons. In addition to this, GMCH supports the Microsoft DirectX* Flexible Vertex Format (FVF), which enables the application to specify a variable length of parameter list obviating the need for sending unused information to the hardware. Strips, Fans, and Indexed Vertices, as well as FVF, improves delivered vertex rate to the setup engine significantly.
Pixel Accurate "Fast" Scissoring and Clipping Operation
The GMCH supports 2D clipping to a scissor rectangle within the drawing window. Objects are clipped to the scissor rectangle, avoiding processing pixels that fall outside the rectangle. GMCH's clipping and scissoring in hardware reduce the need for software to clip objects, and thus improves performance. During the setup stage, the GMCH clips objects to the scissor window. A scissor rectangle accelerates the clipping process by allowing the driver to clip to a bigger region than the hardware renders to. The scissor rectangle needs to be pixel accurate, and independent of line and point width. The GMCH supports a single scissor box rectangle that can be enabled or disabled. The rectangle is defined as an Inclusive box. Inclusive is defined as "draw the pixel if it is inside the scissor rectangle".
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Depth-Bias
The GMCH supports source depth biasing in the setup engine, the depth bias value is specified in the vertex command packet on a per primitive basis. The value ranges from -1 to 1. The depth bias value is added to the z or w value of the vertices. This is used for coplanar polygon priority. If two polygons are to be rendered that are coplanar, due to the inherent precision differences induced by unique x, y and z values, there is no guarantee which polygon will be closer or farther. By using depth bias, it is possible to offset the destination z value (compare value) before comparing with the new z value.
Backface Culling
As part of the setup, the GMCH discards polygons from further processing, if they are facing away from or towards the user's viewpoint. This operation, referred to as "Back Face Culling" is accomplished based on the "clockwise" or "counter-clockwise" orientation of the vertices on a primitive. This can be enabled or disabled by the driver. This is referred to as "Back Face Culling."
5.4.1.2
Scan Converter
The Scan Converter takes the vertex and edge information that is used to identify all pixels that are affected by features being rendered. It works on a per-polygon basis.
Pixel Rasterization Rules
The GMCH supports both OpenGL and D3D pixel rasterization rules to determine whether a pixel is filled by the triangle or line. For both D3D and OpenGL modes, a top-left filling convention for filling geometry is used. Pixel rasterization rule on rectangle primitive is also supported using the top-left fill convention.
5.4.1.3
2D Functionality
The stretch BLT function can stretch source data in the X and Y directions to a destination larger or smaller than the source. Stretch BLT functionality expands a region of memory into a larger or smaller region using replication and interpolation. The stretch BLT function also provides format conversion and data alignment.
5.4.1.4
Texture Engine
The GMCH allows an image, pattern, or video to be placed on the surface of a 3D polygon. The texture processor receives the texture coordinate information from the setup engine and the texture blend information from the scan converter. The texture processor performs texture color or ChromaKey matching, texture filtering (anisotropic, trilinear and bilinear interpolation), and YUV-to-RGB conversions.
Perspective Correct Texture Support
A textured polygon is generated by mapping a 2D texture pattern onto each pixel of the polygon. A texture map is like wallpaper pasted onto the polygon. Since polygons are rendered in perspective, it is important that texture be mapped in perspective as well. Without perspective correction, texture is distorted when an object recedes into the distance.
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Texture Formats and Storage
The GMCH supports up to 32 bits of color for textures.
Texture Decompression
DirectX supports Texture Compression to reduce the bandwidth required to deliver textures. As the textures' average sizes gets larger with higher color depth and multiple textures become the norm, it becomes increasingly important to provide a mechanism to compress textures. Supported Texture decompression formats include DXT1, DXT2, DXT3, DXT4, DXT5, and FXT1.
Texture ChromaKey
ChromaKey describes a method of removing a specific color or range of colors from a texture map before it is applied to an object. For "nearest" texture filter modes, removing a color simply makes those portions of the object transparent (the previous contents of the back buffer show through). For "linear" texture filtering modes, the texture filter is modified if only the non-nearest neighbor texels match the key (range).
Anti-Aliasing
Aliasing is one of the artifacts that degrade image quality. In its simplest manifestation, aliasing causes the jagged staircase effects on sloped lines and polygon edges. Another artifact is the moire patterns that occur as a result of the fact that there is very small number of pixels available on screen to contain the data of a high resolution texture map. More subtle effects are observed in animation, where very small primitives blink in and out of view.
Texture Map Filtering
Many texture mapping modes are supported. Perspective correct mapping is always performed. As the map is fitted across the polygon, the map can be tiled, mirrored in either the U or V directions, or mapped up to the end of the texture and no longer placed on the object (this is known as clamp mode). The way a texture is combined with other object attributes is also definable. The GMCH supports up to 12 Levels-of-Detail (LODs) ranging in size from 2048x2048 to 1x1 texels. (A texel is defined as a texture map element). Textures need not be square. Included in the texture processor is a texture cache, which provides efficient MIP-mapping. The GMCH supports 7 types of texture filtering: 1. Nearest (aka Point Filtering): Texel with coordinates nearest to the desired pixel is used. (This is used if only one LOD is present). 2. Linear (aka Bilinear Filtering): A weighted average of a 2x2 area of texels surrounding the desired pixel are used. (This is used if only one LOD is present). 3. Nearest MIP Nearest (aka Point Filtering): This is used if many LODs are present. The nearest LOD is chosen and the texel with coordinates nearest to the desired pixel are used. 4. Linear MIP Nearest (Bilinear MIP Mapping): This is used if many LODs are present. The nearest LOD is chosen and a weighted average of a 2x2 area of texels surrounding the desired pixel are used (four texels). This is also referred to as Bilinear MIP Mapping. 5. Nearest MIP Linear (Point MIP Mapping): This is used if many LODs are present. Two appropriate LODs are selected and within each LOD the texel with coordinates nearest to the desired pixel are selected. The Final texture value is generated by linear interpolation between the two texels selected from each of the MIP Maps.
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6. Linear MIP Linear (Trilinear MIP Mapping): This is used if many LODs are present. Two appropriate LODs are selected and a weighted average of a 2x2 area of texels surrounding the desired pixel in each MIP Map is generated (four texels per MIP Map). The Final texture value is generated by linear interpolation between the two texels generated for each of the MIP Maps. Trilinear MIP Mapping is used to minimize the visibility of LOD transitions across the polygon. 7. Anisotropic MIP Nearest (Anisotropic Filtering): This is used if many LODs are present. The nearest LOD-1 level will be determined for each of four sub-samples for the desired pixel. These four sub-samples are then bilinear filtered and averaged together. Both D3D (DirectX 6.0) and OGL (Revision1.1) allow support for all these filtering modes.
Multiple Texture Composition
The GMCH also performs multiple texture composition. This allows the combination of two or greater MIP Maps to produce a new one with new LODs and texture attributes in a single or iterated pass. Flexible vertex format support allows multitexturing because it makes it possible to pass more than one texture in the vertex structure.
Bi-Cubic Filter (4x4 Programmable Texture Filter)
A bi-cubic texture filter can be selected instead of the bilinear filter. The implementation is of a 4x4 separable filter with loadable coefficients. A 4x4 filter can be used for providing high-quality up/down scaling of rendered 2D or 3D rendered images.
Cubic Environment Mapping
Environment maps allow applications to render scenes with complex lighting and reflections while significantly decreasing the processor load. There are several methods to generate environment maps (e.g., spherical, circular, and cubic). The GMCH supports cubic reflection mapping over spherical and circular since it is the best choice to provide real-time environment mapping for complex lighting and reflections. Cubic Mapping requires a texture map for each of the 6 cube faces. These can be generated by pointing a camera with a 90-degree field-of-view in the appropriate direction. Per-vertex vectors (normal, reflection or refraction) are interpolated across the polygon and the intersection of these vectors with the cube texture faces is calculated. Texel values are then read from the intersection point on the appropriate face and filtered accordingly.
5.4.1.5
Raster Engine
The Raster Engine is where the color data (e.g., fogging, specular RGB, texture map blending, etc.) is processed. The final color of the pixel is calculated and the RGBA value combined with the corresponding components resulting from the Texture Engine. These textured pixels are modified by the specular and fog parameters. These specular highlighted, fogged, textured pixels are color blended with the existing values in the frame buffer. In parallel, stencil, alpha, and depth buffer tests are conducted that will determine whether the Frame and Depth Buffers will be updated with the new pixel values.
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Texture Map Blending
Multiple textures can be blended together in an iterative process and applied to a primitive. The GMCH allows up to four texture coordinates and texture maps to be specified onto the same polygon. Also, the GMCH supports using a texture coordinate set to access multiple texture maps. State variables in multiple texture are bound to texture coordinates, texture map or texture blending.
Combining Intrinsic and Specular Color Components
The GMCH allows an independently specified and interpolated "specular RGB" attribute to be added to the post-texture blended pixel color. This feature provides a full RGB specular highlight to be applied to a textured surface, permitting a high quality reflective colored lighting effect not available in devices which apply texture after the lighting components have been combined. If specular-add state variable is disabled, only the resultant colors from the map blending are used. If this state variable is enabled, RGB values from the output of the map blending are added to values for RS, GS, BS on a component by component basis.
Color Shading Modes
The raster engine supports the flat and Gouraud shading modes. These shading modes are programmed by the appropriate state variables issued through the command stream. Flat shading is performed by smoothly interpolating the vertex intrinsic color components (red, green, blue), Specular (R, G, B), Fog, and Alpha to the pixel, where each vertex color has the same value. The setup engine substitutes one of the vertex's attribute values for the other two vertices attribute values thereby creating the correct flat shading terms. This condition is set up by the appropriate state variables issued prior to rendering the primitive. OpenGL and D3D use a different vertex to select the flat shaded color. This vertex is defined as the "provoking vertex". In the case of strips/fans, after the first triangle, attributes on every vertex that define a primitive is used to select the flat color of the primitive. A state variable is used to select the "flat color" prior to rendering the primitive. Gouraud shading is performed by smoothly interpolating the vertex intrinsic color components (red, green, blue). Specular (RGB), fog, and alpha to the pixel, where each vertex color has a different value. All the attributes can be selected independently to one of the shading mode by setting the appropriate value state variables.
Color Dithering
Color Dithering helps to hide color quantization errors. Color Dithering takes advantage of the human eye's propensity to "average" the colors in a small area. Input color, alpha, and fog components are converted from 8-bit components to 5- or 6- bit component by dithering. Dithering is performed on blended textured pixels. In 32-bit mode, dithering is not performed on the components.
Vertex and Per Pixel Fogging
Fogging is used to create atmospheric effects (e.g., low visibility conditions in flight simulator-type games). It adds another level of realism to computer-generated scenes. Fog can be used for depth cueing or hiding distant objects. With fog, distant objects can be rendered with fewer details (less polygons), thereby improving the rendering speed or frame rate. Fog is simulated by attenuating
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the color of an object with the fog color as a function of distance. The greater the distance, the higher the density (lower visibility for distant objects). There are two ways to implement the fogging technique: per-vertex (linear) fogging and per-pixel (non-linear) fogging. The per-vertex method interpolates the fog value at the vertices of a polygon to determine the fog factor at each pixel within the polygon. This method provides realistic fogging as long as the polygons are small. With large polygons (e.g., a ground plane depicting an airport runway), the per-vertex technique results in unnatural fogging. The GMCH supports both types of fog operations, vertex and per pixel or table fog. If fog is disabled, the incoming color intensities are passed unchanged to the destination blend unit.
Alpha Blending (Frame Buffer)
Alpha Blending adds the material property of transparency or opacity to an object. Alpha blending combines a source pixel color (RSGSBS) and alpha (AS) component with a destination pixel color (RDGDBD) and alpha (AD) component. For example, this is so that a glass surface on top (source) of a red surface (destination) would allow much of the red base color to show through. Blending allows the source and destination color values to be multiplied by programmable factors and then combined via a programmable blend function. The combined and independent selection of factors and blend functions for color and alpha are supported.
DXn and OGL Logic Ops
Both APIs provide a mode to use bitwise ops in place of alpha blending. This is used for rubberbanding (i.e., draw a rubber band outline over the scene using an XOR operation). Drawing it again restores the original image without having to do a potentially expensive redraw.
Color Buffer Formats: 8-, 16-, or 32-bits per pixel (Destination Alpha)
The Raster Engine supports 8-bit, 16-bit, and 32-bit Color Buffer Formats. The 8-bit format is used to support planar YUV420 format, which is used only in motion compensation and arithmetic stretch format. The bit format of Color and Z will be allowed to mix. The GMCH supports both double and triple buffering, where one buffer is the primary buffer used for display and one or two are the back buffer(s) used for rendering. The frame buffer of the GMCH contains at least two hardware buffers--the Front Buffer (display buffer) and the Back Buffer (rendering buffer). While the back buffer may actually coincide with (or be part of) the visible display surface, a separate (screen or window-sized) back buffer is used to permit double-buffered drawing. That is, the image being drawn is not visible until the scene is complete and the back buffer made visible (via an instruction) or copied to the front buffer (via a 2D BLT operation). Rendering to one and displaying from the other remove the possibility of image tearing. This also speeds up the display process over a single buffer. Additionally, triple back buffering is also supported. The Instruction set of the GMCH provides a variety of controls for the buffers (e.g., initializing, flip, clear, etc.).
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Depth Buffer
The Raster Engine is able to read and write from this buffer and use the data in per fragment operations that determine whether resultant color and depth value of the pixel for the fragment are to be updated or not. Typical applications for entertainment or visual simulations with exterior scenes require far/near ratios of 1000 to 10000. At 1000, 98% of the range is spent on the first 2% of the depth. This can cause hidden surface artifacts in distant objects, especially when using 16-bit depth buffers. A 24-bit Z-buffer provides 16 million Z-values as opposed to only 64 K with a 16-bit Z-buffer. With lower Z-resolution, two distant overlapping objects may be assigned the same Z-value. As a result, the rendering hardware may have a problem resolving the order of the objects, and the object in the back may appear through the object in the front. By contrast, when w (or eye-relative z) is used, the buffer bits can be more evenly allocated between the near and far clip planes in world space. The key benefit is that the ratio of far and near is no longer an issue, allowing applications to support a maximum range of miles, yet still get reasonably accurate depth buffering within inches of the eye point. The GMCH supports a flexible format for the floating-point W buffer, wherein the number of exponent bits is programmable. This allows the driver to determine variable precision as a function of the dynamic range of the W (screen-space Z) parameter. The selection of depth buffer size is relatively independent of the color buffer. A 16-bit Z/W or 24-bit Z/W buffer can be selected with a 16-bit color buffer. Z buffer is not supported in 8-bit mode.
Stencil Buffer
The Raster Engine provides 8-bit stencil buffer storage in 32-bit mode and the ability to perform stencil testing. Stencil testing controls 3D drawing on a per pixel basis, conditionally eliminating a pixel on the outcome of a comparison between a stencil reference value and the value in the stencil buffer at the location of the source pixel being processed. They are typically used in multipass algorithms to achieve special effects (e.g., decals, outlining, shadows, and constructive solid geometry rendering).
Projective Textures
The GMCH supports two, simultaneous projective textures at full rate processing, and four textures at half rate. These textures require three floating point texture coordinates to be included in the FVF format. Projective textures enable special effects (e.g., projecting spot light textures obliquely onto walls, etc.).
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5.4.2
2D Engine
The GMCH contains BLT functionality, and an extensive set of 2D instructions. To take advantage of the 3D drawing engine's functionality, some BLT functions (e.g., Alpha BLTs, arithmetic (bilinear) stretch BLTs, rotations, transposing pixel maps, limited color space conversion, and DIBs make use of the 3D renderer.
GMCH VGA Registers
The 2D registers are a combination of registers defined by IBM when the Video Graphics Array (VGA) was first introduced and others that Intel has added to support graphics modes that have color depths, resolutions, and hardware acceleration features that go beyond the original VGA standard.
Logical 128-bit Fixed BLT and 256-bit Fill Engine
Use of this BLT engine accelerates the Graphical User Interface (GUI) of Microsoft Windows* operating systems. The 128-bit GMCH BLT Engine provides hardware acceleration of block transfers of pixel data for many common Windows operations. The term BLT refers to a block transfer of pixel data between memory locations. The BLT engine can be used for the following:
* Move rectangular blocks of data between memory locations * Data Alignment * Perform logical operations (raster ops)
The rectangular block of data does not change as it is transferred between memory locations. The allowable memory transfers are between:
* cacheable and system memory and frame buffer memory * frame buffer memory and frame buffer memory * within system memory.
Data to be transferred can consist of regions of memory, patterns, or solid color fills. A pattern will always be 8x8 pixels wide and may be 8, 16, or 32 bits per pixel. The GMCH BLT engine has the ability to expand monochrome data into a color depth of 8, 16, or 32 bits. BLTs can be either opaque or transparent. Opaque transfers, move the data specified to the destination. Transparent transfers, compare destination color to source color and write according to the mode of transparency selected. Data is horizontally and vertically aligned at the destination. If the destination for the BLT overlaps with the source memory location, the GMCH can specify which area in memory to begin the BLT transfer. Hardware is included for all 256 raster operations (Source, Pattern, and Destination) defined by Microsoft, including transparent BLT. The GMCH has instructions to invoke BLT and STRBLT operations, permitting software to set up instruction buffers and use batch processing. The GMCH can perform hardware clipping during BLTs.
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5.4.3
Video Engine
Hardware Motion Compensation
The Motion Compensation (MC) process consists of reconstructing a new picture by predicting (either forward, backward, or bidirectionally) the resulting pixel colors from one or more reference pictures. The GMCH receives the video stream and implements motion compensation and subsequent steps in hardware. Performing Motion Compensation in hardware reduces the processor demand of software-based MPEG-2 decoding, and thus improves system performance. The motion compensation functionality is overloaded onto the texture cache and texture filter. The texture cache is used to typically access the data in the reconstruction of the frames and the filter is used in the actual motion compensation process. To support this overloaded functionality the texture cache additionally supports the following input formats:
* YUV420 planar
Sub-Picture Support
Sub-picture is used for two purposes; one is Subtitles for movie captions, etc., which are superimposed on a main picture, and another is for Menus to provide some visual operation environments for the user of the player. DVD allows movie subtitles to be recorded as Sub-pictures. On a DVD disc, it is called "Subtitle" because it has been prepared for storing captions. Since the disc can have a maximum of 32 tracks for Subtitles, they can be used for various applications; for example, as Subtitles in different languages or other information to be displayed. There are two kinds of Menus, the System Menus and other In-Title Menus. First, the System Menus are displayed and operated at startup of or during the playback of the disc or from the stop state. Second, In-Title menus can be programmed as a combination of Sub-picture and Highlight commands to be displayed during playback of the disc. The GMCH supports sub-picture for DVD and DBS by mixing the two video streams via alpha blending. Unlike color keying, alpha blending provides a softer effect and each pixel that is displayed is a composite between the two video stream pixels. The GMCH can use four methods when dealing with sub-pictures. The flexibility enables the GMCH to work with all sub-picture formats.
5.4.4
Planes
A plane consists of a rectangular shaped image that has characteristics such as source, size, position, method, and format. These planes get attached to source surfaces that are rectangular memory surfaces with a similar set of characteristics. They are also associated with a particular destination pipe.
5.4.4.1
Cursor Plane
The cursor plane is one of the simplest display planes. With a few exceptions, this plane has a fixed size of 64x64 and a fixed Z-order (top). In legacy modes, cursor can cause the display data below it to be inverted.
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5.4.4.2
Overlay Plane
The overlay engine provides a method of merging either video capture data (from an external video capture device) or data delivered by the processor, with the graphics data on the screen. The source data can be mirrored horizontally, vertically, or both.
Source/Destination Color Keying/ChromaKeying
Overlay source/destination ChromaKeying enables blending of the overlay with the underlying graphics background. Destination color keying/ChromaKeying can be used to handle occluded portions of the overlay window on a pixel by pixel basis that is actually an underlay. Destination ChromaKeying would only be used for YUV passthrough to TV. Destination color keying supports a specific color (8- or 15-bit) mode as well as 32-bit alpha blending. Source color keying/ChromaKeying is used to handle transparency based on the overlay window on a pixel-by-pixel basis. This is used when "blue screening" an image to overlay the image on a new background later.
Gamma Correction
To compensate for overlay color intensity loss due to the non-linear response between display devices, the overlay engine supports independent gamma correction. This allows the overlay data to be converted to linear data or corrected for the display device when not blending.
YUV-to-RGB Conversion
The format conversion can be bypassed in the case of RGB source data. The format conversion assumes that the YUV data is input in the 4:4:4 format and uses the full range scale.
Maximum Resolution and Frequency
The maximum frequency supported by the overlay logic is 170 MHz. The maximum resolution is dependent on a number of variables.
Deinterlacing Support
For display on a progressive computer monitor, interlaced data that has been formatted for display on interlaced monitors (TV), needs to be de-interlaced. The simple approaches to de-interlacing create unwanted display artifacts. More advanced de-interlacing techniques have a large cost associated with them. The compromise solution is to provide a low cost but effective solution and enable both hardware and software based external solutions. Software based solutions are enabled through a high bandwidth transfer to system memory and back. Dynamic Bob and Weave. Interlaced data that originates from a video camera creates two fields that are temporally offset by 1/60 of a second. There are several schemes to deinterlace the video stream: line replication, vertical filtering, field merging, and vertical temporal filtering. Field merging takes lines from the previous field and inserts them into the current field to construct the frame - this is known as Weaving. This is the best solution for images with little motion; however, showing a frame that consists of the two fields will have serration or feathering of moving edges when there is motion in the scene. Vertical filtering or "Bob" interpolates adjacent lines rather replicating the nearest neighbor. This is the best solution for images with motion; however, it will have reduced spatial resolution in areas that have no motion and introduces jaggies. In absence of any other deinterlacing, these form the baseline and are supported by the GMCH.
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Scaling Filter and Control
The scaling filter has three vertical taps and five horizontal taps. Arbitrary scaling (per pixel granularity) for any video source (YUV422 or YUV420) format is supported. The overlay logic can scale an input image up to 1600X1200 with no major degradation in the filter used as long as the maximum frequency limitation is met. Display resolution and refresh rate combinations, where the dot clock is greater than the maximum frequency, require the overlay to use pixel replication.
5.4.5
Pipes
The display consists of a single pipe. The pipe can operate in a single-wide or "double-wide" mode at 2X graphics core clock though, it is effectively limited by its display port (350 MHz maximum). The primary display plane and the cursor plane provides a "double wide" mode to feed the pipe.
Clock Generator Units (DPLL)
The clock generator units provide a stable frequency for driving display devices. It operates by converting an input reference frequency into an output frequency. The timing generators take their input from internal DPLL devices that are programmable to generate pixel clocks in the range of 25-350 MHz. Accuracy for VESA timing modes is required to be within 0.5%. The DPLL can take a reference frequency from the external reference input (e.g., DREFCLK) for the TV clock input (DVOBC_CLKIN).
5.5
Display Interfaces
The GMCH has three display ports; one analog and two digital. Each port can transmit data according to one or more protocols. The digital ports are connected to an external device that converts one protocol to another. Examples of this are TV encoders, external DACs, LVDS transmitters, and TMDS transmitters. Each display port has control signals that may be used to control, configure, and/or determine the capabilities of an external device. The GMCH has one dedicated display port, the analog port. DVO B and DVO C are multiplexed with the AGP interface and are not available if an external AGP graphics device is in use. When a system uses an AGP connector, DVO ports B and C can be used via an ADD (AGP Digital Display) card. Ports B and C can also operate in dual-channel mode, where the data bus is connected to both display ports, allowing a single device to take data at twice the pixel rate. The GMCH's analog port uses an integrated 350 MHz RAMDAC that can directly drive a standard progressive scan analog monitor up to a resolution of 2048x1536 pixels with 32-bit color at 75 Hz. The GMCH's DVO ports are each capable of driving a 165 MHz pixel clock. Each port is capable of driving a digital display up to 1600x1200 @ 60Hz. When in dual-channel mode, the GMCH can drive a flat panel up to 2048x1536 @ 60Hz or dCRT/HDTV up to 1920x1080 @ 85Hz. The GMCH is compliant with Digital Visual Interface (DVI) Specification, Revision 1.0. When combined with a DVI compliant external device and connector, the GMCH has a high-speed interface to a digital display (e.g., flat panel or digital CRT).
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Table 32. Display Port Characteristics
Parameter Interface Protocol S I G N A L S HSYNC VSYNC BLANK STALL Field Display_Enable No No No No Square(1) RGB 0.7 V p-p NA 350 Mpixel Analog RGB DDC1/DDC2B No VGA/DVI-I 1.5 V Differential 165/330 Mpixel RGB 8:8:8 YUV 4:4:4 DDC2B TMDS/LVDS Transmitter /TV Encoder DVI/CVBS/S-Video/Component/SCART 1.5 V Analog RGB DAC Digital Port B DVO 2.0 Yes Enable/Polarity Yes Enable/Polarity Yes(1) Yes Yes Yes(1) Yes Yes Yes(1) Digital Port C DVO 2.0
Image Aspect Ratio Pixel Aspect Ratio Voltage Clock Max Rate Format Control Bus External Device Connector
Programmable and typically 1.33:1 or 1.78:1
NOTE: 1. Single signal software selectable between display enable and Blank#.
5.5.1
Analog Display Port Characteristics
The analog display port provides a RGB signal output along with a HSYNC and VSYNC signal. There is an associated DDC signal pair that is implemented using GPIO pins dedicated to the analog port. The intended target device is for a CRT-based monitor with a VGA connector. Display devices (e.g., LCD panels with analog inputs) may work satisfactory but no functionality has been added to the signals to enhance that capability.
Table 33. Analog Port Characteristics
Signal Port Characteristic Voltage Range RGB Monitor Sense Analog Copy Protection Sync on Green Voltage Enable/Disable HSYNC VSYNC Polarity adjust Composite Sync Support Special Flat Panel Sync Stereo Sync DDC Voltage Control Support 0.7 V p-p only Analog Compare No No 3.3 V Port control VGA or port control No No No Externally buffered to 5 V Through GPIO interface
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Integrated RAMDAC
The display function contains a RAM-based Digital-to-Analog Converter (RAMDAC) that transforms the digital data from the graphics and video subsystems to analog data for the CRT monitor. GMCH's integrated 350 MHz RAMDAC supports resolutions up to 2048 x 1536 @ 75 Hz. Three 8-bit DACs provide the RED, GREEN, and BLUE signals to the monitor.
Sync Signals
HSYNC and VSYNC signals are digital and conform to TTL signal levels at the connector. Since these levels cannot be generated internal to the device, external level shifting buffers are required. These signals can be polarity adjusted and individually disabled in one of the two possible states. The sync signals should power up disabled in the high state. No composite sync or special flat panel sync support is included.
VESA/VGA Mode
VESA/VGA mode provides compatibility for pre-existing software that set the display mode using the VGA CRTC registers. Timings are generated based on the VGA register values and the timing generator registers are not used.
DDC (Display Data Channel)
DDC is a standard defined by VESA. Its purpose is to allow communication between the host system and display. Both configuration and control information can be exchanged allowing plugand-play systems to be realized. Support for DDC 1 and 2 is implemented. The GMCH uses the DDCA_CLK and DDCA_DATA to communicate with the analog monitor. The GMCH generates these signals at 2.6 V. External pull-up resistors and level shifting circuitry should be implemented on the board. The GMCH implements a hardware GMBus controller that can be used to control these signals. This allows higher speed transactions (up to 400 kHz) on theses lines than previous software centric `bit-bashing' techniques.
5.5.2
Digital Display Interface
The GMCH has several options for driving digital displays. The GMCH contains two DVO ports that are multiplexed on the AGP interface. When an external AGP graphics accelerator is not present, the GMCH can use the multiplexed DVO ports to provide extra digital display options. These additional digital display capabilities may be provided through an ADD card that is designed to plug in to a 1.5 V AGP connector.
5.5.2.1
Digital Display Channels - Intel(R) DVOB and Intel(R) DVOC
The GMCH has the capability to support digital display devices through two DVO ports multiplexed with the AGP signals. When an external graphics accelerator is used via AGP, these DVO ports are not available. Refer to Section 2.5.6 for a detailed description of the shared DVO signals. The shared DVO ports each support a pixel clock up to 165 MHz and can support a variety of transmission devices. When using a 24-bit external transmitter, it will be possible to pair the two DVO ports in dual-channel mode to support a single digital display with higher resolutions and refresh rates. In this mode, the GMCH is capable of driving a pixel clock up to 330 MHz.
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The GMCH multiplexes an ADD_DETECT signal with the GPAR signal on the AGP bus. This signal acts as a strap and indicates whether the interface is in AGP or DVO mode. The GMCH has an internal pull-up on this signal that will naturally pull it high. If an ADD card is present, the signal will be pulled low on the ADD card and the AGP/DVO multiplex select bit in the GMCHCFG register will be toggled to DVO mode. Motherboards that do not use an AGP connector should have a pull-down resistor on ADD_DETECT if they have digital display devices connected to the AGP/DVO interface. 5.5.2.1.1 ADD Card When an 865G chipset platform uses an AGP connector, the multiplexed DVO ports may be used via an ADD card. The ADD card will be designed to fit a standard 1.5 V AGP connector. 5.5.2.1.2 TMDS Capabilities The GMCH is compliant with Digital Visual Interface (DVI) Specification, Revision 1.0. When combined with a DVI compliant external device and connector, the GMCH has a high-speed interface to a digital display (e.g., flat panel or digital CRT). When combining the two multiplexed DVO ports, the GMCH can drive a flat panel up to 2048x1536 or a dCRT/HDTV up to 1920x1080. Flat Panel is a fixed resolution display. The GMCH supports panel fitting in the transmitter, receiver or an external device, but has no native panel fitting capabilities. The GMCH, however, provides unscaled mode where the display is centered on the panel. 5.5.2.1.3 LVDS Capabilities The GMCH can use the multiplexed DVO ports to drive an LVDS transmitter. The flat panel is a fixed resolution display. While the GMCH supports panel fitting in the transmitter, receiver, or an external device, it has no native panel fitting capabilities. The GMCH, however, provides unscaled mode where the display is centered on the panel. The GMCH supports scaling in the LVDS transmitter through the DVOB (or C)_STL pin, which is multiplexed with DVOB (or C)_FLD. 5.5.2.1.4 TV-Out Capabilities While traditional TVs are not digital displays, the GMCH uses a digital display channel to communicate with a TV-Out transmitter. For this reason, the GMCH considers a TV-Output to be a digital display. GMCH supports NTSC/PAL/SECAM standard definition formats. The GMCH generates the proper timing for the external encoder. The external encoder is responsible for generation of the proper format signal. Since the multiplexed DVO interface is 1.5 V, care should be taken to ensure that the TV encoder is operational at that signaling voltage. A NTSC/PAL/SECAM display on the TV-Out port can be configured to be the boot device. It is necessary to ensure that appropriate BIOS support is provided. The TV-Out interface on the GMCH is addressable as a master device. This allows an external TV encoder device to drive a pixel clock signal on DVOBC_CLKINT# that the GMCH uses as a reference frequency. The frequency of this clock is dependent on the output resolution required. Data is driven to the encoder across 12 data lines, along with a clock pair and sync signals. The encoder can expect a continuous flow of data from GMCH because data will not be throttled.
Flicker Filter and Overscan Compensation
The overscan compensation scaling and the flicker filter is done in the external TV encoder chip. Care must be taken to allow for support of TV sets with high performance de-interlacers and progressive scan displays connected to by way of a non-interlaced signal. Timing will be generated with pixel granularity to allow more overscan ratios to be supported.
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Direct YUV from Overlay
When source material is in the YUV format and is destined for a device that can take YUV format data in, it is desired to send the data without converting it to RGB. This avoids the truncation errors associated with multiple color conversion steps. The common situation is that the overlay source data is in the YUV format and bypasses the conversion to RBG as it is sent to the TV port directly.
Sync Lock Support
Sync lock to the TV is accomplished using the external encoders PLL combined with the display phase detector mechanism. The availability of this feature is determined by which external encoder is in use.
Analog Content Protection
Analog content protection is provided through the external encoder using Macrovision 7.01. DVD software must verify the presence of a Macrovision TV encoder before playback continues. Simple attempts to disable the Macrovision operation must be detected.
Connectors
Target TV connectors support includes the CVBS, S-Video, Component, and SCART connectors. The external TV encoder in use will determine the method of support. 5.5.2.1.5 DDC (Display Data Channel) The multiplexed digital display interface uses the MDVI_CLK and MDVI_DATA signals to interrogate the panel. The GMCH supports the DDC2B protocol to initiate the transfer of EDID data. The multiplexed digital display interface uses the M_I2C bus to interrogate the external transmitter. A third set of signals (MDDC_CLK and MDDC_DATA) is available for a variety of purposes. They can be used as a second DDC pair when two TMDS transmitters are used, or as a second I2C pair if there are multiple devices (e.g., PROM and DVO device) that need I2C and there is a speed or addressing conflict. The GMCH implements a hardware GMBus controller that can be used to control these signals. This allows higher speed transactions (up to 400 kHz) on theses lines than was allowed with previous software centric `bit-bashing' techniques. 5.5.2.1.6 Optional High-Speed (Dual-Channel) Interface The multiplexed digital display ports can operate in either two 12-bit port modes or one 24-bit mode. The 24-bit mode uses the 12-bit DVOC data pins combined with the DVOB data pins to make a 24-bit bus. This doubles the transfer rate capabilities of the port. In the single port case, horizontal periods have a granularity of a single pixel clock; in the double case, horizontal periods have a granularity of two pixel clocks. In both cases, data is transferred on both edges of the differential clock. The GMCH can output the data in a high-low fashion, with the lower 12 bits of the pixel on DVOC and the upper 12 bits of data on DVOB. In this manner, the GMCH transfers an entire pixel per clock edge (2 pixels per clock). In addition to this, the GMCH also can transfer dual-channel data in odd-even format. In this mode, the GMCH transfers all odd pixels on one DVO, and all even pixels on the other DVO. In this format, each DVO will see both the high and low half of the pixel, but will only see half of the pixels transferred. As in high-low mode, 2 full pixels are transferred per clock period. This ordering can be modified through DVO control registers.
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5.5.2.1.7
Intel(R) DVO Modes In single-channel mode, the order of pixel transmission (high-low vs. low-high) can be adjusted via the data ordering bit of that DVO's control register. As mentioned above, when in dual-channel mode, the GMCH can transmit data in a high-low or odd-even format. In high-low mode, software can choose which half goes to which port. A 0 = DVOB Lo/DVOC Hi, and a 1 = DVOB Hi/ DVOC Lo. In odd/even mode, the odd pixels will always go out to DVOC and even pixels will always go out to DVOB. Which DVO port is even and which is odd cannot be switched, but the data order bit can be used to change the active data order within the even and odd pixels. The GMCH considers the first pixel to be pixel zero and will send it out to DVOB.
5.5.3
Synchronous Display
Microsoft Windows* Me, Windows* 2000, and Windows* XP operating systems have enabled support for multi-monitor display. Synchronous mode displays the same information on multiple displays. Since the GMCH has several display ports available for its single pipe, it can support a synchronous display on 2 or 3 displays, unless one of the displays is a TV. No synchronous display is available when a TV is in use. The GMCH cannot drive multiple displays concurrently (different data or timings). In addition, the GMCH cannot operate in parallel with an external AGP device. The GMCH can, however, work in conjunction with a PCI graphics adapter.
5.6
Power Management
The GMCH power management support includes:
* * * *
ACPI supported System States: S0, S1 (desktop), S3, S4, S5, C0, C1, C2 (desktop) Graphics States: D0, D3 Monitor States: D0, D1, D2, D3
5.6.1
Supported ACPI States
GMCH supports the following ACPI States:
* Graphics
-- D0 -- D3 Hot -- D3 Cold Full on, display active. GMCH power on. Display off. Configuration registers, state, and main memory contents retained. Power off. Full On. Auto Halt. Stop Grant. Clk to processor still running. Clock stopped to processor core.
* Processor
-- C0 -- C1 -- C2-Desktop
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* System
-- G0/S0 -- G1/S1 -- G1/S2 -- G1/S3 -- G1/S4 -- G2/S5 -- G3 Full On. Stop Grant, Desktop S1, same as C2. Not supported. Suspend to RAM (STR). Power and context lost to chipset. Suspend to Disk (STD). All power lost (except wakeup logic on ICH5). Soft off. Requires total system reboot. Mechanical Off. All power lost (except real time clock).
5.7
Thermal Management
The GMCH implements the following thermal management mechanisms. The mechanisms will manage the read and write cycles of the system memory interface, thus, ensuring that the temperature can return to the normal operating range.
Hardware-Based Thermal Management
The number of hexwords transferred over the DRAM interface are tracked per row. The tracking mechanism takes into account that the DRAM devices consume different levels of power based on cycle type (i.e., page hit/miss/empty). If the programmed threshold is exceeded during a monitoring window, the activity on the DRAM interface is reduced. This helps in lowering the power and temperature.
Software-Based Thermal Management
This is used when the external thermal sensor in the system interrupts the processor to engage a software routine for thermal management.
5.7.1
External Thermal Sensor Interface Overview
An external thermal sensor with a serial interface (e.g., the National Semiconductor LM77, LM87, or other) may be placed next to DDR DIMM (or any other appropriate platform location), or a remote thermal diode may be placed next to the DIMM (or any other appropriate platform location) and connected to the external thermal sensor. The external sensor can be connected to the ICH5 via the SMBus interface to allow programming and setup by BIOS software over the serial interface. The external sensor's output should include an active-low open-drain signal indicating an over-temp condition (e.g., LM77 T_CRIT# or INT# in comparator mode). The sensor's output remains asserted for as long as the over-temp condition exists and deasserts when the temperature has returned to within normal operating range. This external sensor output will be connected to the GMCH input (EXTTS#) and will trigger a preset interrupt and/or read-throttle on a level-sensitive basis. Additional external thermal sensor's outputs, for multiple sensors, can be wire-OR'd together to allow signaling from multiple sensors that are physically separated. Software can, if necessary, distinguish which DIMM(s) is the source of the over-temp through the serial interface. However, since the DIMMs are located on the same memory bus data lines, any GMCH-base read throttle will apply equally.
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Note:
The use of external sensors that include an internal pull-up resistor on the open-drain thermal trip output is discouraged; however, it may be possible depending on the size of the pull-up and the voltage of the sensor.
Figure 14. Platform External Sensor
V EXTTS# GMCH R(1)
Processor
DIMM
THERM# TS TS
Intel(R) ICH5
DIMM
SMBus
SMBdata SMBclock
NOTE: 1. External pull-up R is associated with the voltage rail of the GMCH input.
5.7.1.1
External Thermal Sensor Usage Model
There are several possible usage models for an external thermal sensor:
* External sensor(s) used for characterization only, not for normal production * Sensor on the DIMMs for temperature in OEM platform and use the results to permanently set
read throttle values in the BIOS
* Sensor on the GMCH for temperature in OEM platform and use the results to permanently set
write throttle values in the BIOS
* External sensor(s) used for dynamic temperature feedback control in production releases * Sensor on DIMMs, which can be used to dynamically control read throttling * Sensor on GMCH, which can be used to dynamically control write throttling
The advantage of the characterization model is the Bill-Of-Material (BOM) cost, whereas the potential advantage of the dynamic model is that retail customers may be able to experience higher peak performance since the throttle values are not forced to encompass worse case environmental conditions. Characterization tools (e.g., CTMI and Maxband) can be made to work either with external or internal sensors.
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5.8
Clocking
The GMCH has the following clocks:
* * * * *
100/133/200 spread spectrum, Low voltage (0.7 V) Differential HCLKP/HCLKN for FSB 66.667 MHz, spread spectrum, 3.3 V GCLKIN for Hub Interface and AGP 48 MHz, non-spread spectrum, 3.3 V DREFCLK for the Display frequency syntheses 12 pairs SDRAM output clocks (SCMCLK_x[5:0] and SCMDCLK_x[5:0]# for both channels A and B) Up to 85 MHz, 1.5 V DVOBC_CLKINT for TV-Out mode only.
The GMCH has inputs for a low voltage, differential pair of clocks called HCLKP and HCLKN. These pins receive a host clock from the external clock synthesizer. This clock is used by the host interface and system memory logic (Host Clock Domain). The graphics engine also uses this clock. AGP and hub interface are synchronous to each other and are driven from the 66 MHz clock. The Graphics core and display interfaces are asynchronous to the rest of the GMCH. Figure 15. Intel(R) 865G Chipset System Clocking Block Diagram
Processor
Low Voltage Differential Clocks Low Voltage Differential Clocks DDR Differential Pairs 266/333/400 MHz DDR
DIMM 0
DIMM 1
DIMM 2
100/133/200 MHz
133/166/200 MHz
AND/OR AGP8X
DDR Differential Pairs
GMCH
Core PLL
DPLL 24-350 MHz
48 MHz DOT
66 MHz
66 MHz
33 MHz 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz 66 MHz
PCI Slot 0 PCI Slot 1 PCI Slot 2 PCI Dev 1 PCI Dev 2 PCI Dev 3 PCI Dev 4 PCI Dev 5
CK 409
Buffer Section /2
Main PLL 400 MHz
14 MHz OSC 100/ 133/200 MHz ITP
48 MHz PLL
48 MHz USB 14 MHz 33 MHz APIC 48 MHz DOT
Intel(R) ICH5
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DIMM 3
Host PLL
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Electrical Characteristics
Electrical Characteristics
6
This chapter contains the maximum ratings, thermal characteristics, power characteristics, and DC characteristics for the GMCH.
6.1
Absolute Maximum Ratings
Table 34 lists the GMCH's maximum environmental stress ratings. Functional operation at the absolute maximum and minimum is neither implied nor guaranteed. Functional operating parameters are listed in the DC characteristics tables.
Warning:
Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operating beyond the "operating conditions" is not recommended and extended exposure beyond "operating conditions" may affect reliability.
Table 34. Absolute Maximum Ratings
Symbol VCC VCC_AGP VCCA_AGP VTT VCC_DDR VCCA_DDR VCC_DAC VCCA_DAC VCCA_DPLL VCCA_FSB 1.5 V Core Supply 1.5 V AGP Supply (AGP mode) 1.5 V Analog AGP Supply VTT Supply 2.6 V DDR System Memory Interface Supply 1.5 V Analog Supply for System Memory DLLs 3.3 V DAC Supply 1.5 V DAC Analog Supply 1.5 V Display PLL Analog Supply 1.5 V Host PLL Analog Supply Parameter Min -0.3 -0.3 -0.3 -0.3 -0.5 -0.3 -0.3 -0.3 -0.3 -0.3 Max 1.75 1.75 1.75 1.75 3 1.75 3.6 1.65 1.75 1.75 Unit V V V V V V V V V V
6.2
Thermal Characteristics
Refer to the Intel(R) 865G/865GV/865PE/865P Chipset Thermal Design Guide for thermal characteristics.
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6.3
Power Characteristics
Table 35. Power Characteristics
Symbol IVCC IVCC IVCC_AGP IVCC_AGP IVCCA_AGP IVTT IVCC_DDR IVCCA_DDR IVCC_DAC IVCCA_DAC IVCCA_DPLL IVCCA_FSB IVCC_SUS_2.6 Parameter 1.5 V Core Supply Current (integrated graphics) 1.5 V Core Supply Current (discrete graphics) 1.5 V AGP Supply Current (AGP mode) 1.5 V AGP Supply Current (DVO mode) 1.5 V Analog AGP Supply Current VTT Supply Current 2.6 V DDR System Memory Interface Supply Current 1.5 V Analog Supply Current for System Memory DLLs 3.3 V DAC Supply Current 1.5 V DAC Analog Supply Current 1.5 V Display PLL Analog Supply Current 1.5 V Host PLL Analog Supply Current 2.6 V Standby Supply Current Max 4.38 2.88 0.37 0.18 0.01 1.6 5.7 1.2 0.2 0.07 0.01 0.05 0.25 Unit A A A A A A A A A A A A A Notes 1,2,3 1,2 2 2
NOTES: 1. The hub interface and CSA interface supply currents are included in the 1.5 V VCC core supply current. 2. VCC and VCC_AGP current levels may happen simultaneously and can be summed into one 1.5 V supply. 3. This specification applies to the GMCH using integrated graphics.
6.4
Signal Groups
The signal description includes the type of buffer used for the particular signal: AGTL+ Open Drain AGTL+ interface signal. Refer to the AGTL+ I/O Specification for complete details. The GMCH integrates most AGTL+ termination resistors. AGP interface signals. These signals are compatible with AGP 2.0 1.5 V and AGP 3.0 0.8V Signaling Environment DC and AC Specifications. The buffers are not 3.3 V tolerant. (DVO signals use the same buffers as AGP) Hub Interface 1.5 V CMOS buffers. Stub Series Terminated Logic 2.6 V compatible signals. DDR system memory 2.6 V CMOS buffers. 2.6 V and 3.3 V Miscellaneous buffers.
AGP
HI15 SSTL_2 Miscellaneous
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Table 36. Signal Groups (Sheet 1 of 2)
Signal Group Signal Type Signals Notes1
AGP Interface Signal Groups (only AGP 3.0 naming convention listed) (a) (b) (c) (d) AGP I/O AGP Input AGP Output AGP Miscellaneous GADSTBF[1:0], GADSTBS[1:0], GFRAME, GIRDY, GTRDY, GSTOP, GDEVSEL, GAD[31:0], GCBE[3:0], GPAR/ADD_DETECT, DBI_HI, DBI_LO GSBA[7:0]#, GRBF, GWBF, GSBSTBF, GSBSTBS, GREQ GST[2:0], GGNT GVREF, GRCOMP/DVOBCRCOMP, GVSWING
Hub Interface Signal Groups (e) (f) HI15 I/O Hub Interface Miscellaneous HI[10:0], HISTRS, HISTRF HI_SWING, HI_VREF, HI_RCOMP
CSA Interface Signal Groups (e) (f) HI15 I/O CSA Interface Miscellaneous CI[10:0], CISTRS, CISTRF CI_SWING, CI_VREF, CI_RCOMP
Host Interface Signal Groups (g) (h) (i) (j) (k) AGTL+ I/O AGTL+ Input AGTL+ Output CMOS Host Clock Input Host Miscellaneous ADS#, BNR#, DBSY#, DINV[3:0]#, DRDY#, HA[31:3]#, HADSTB[1:0] #, HD[63:0]#,HDSTBP[3:0]#, HDSTBN[3:0]#, HIT#, HITM#, HREQ[4:0]#, PROCHOT# HLOCK# BPRI#, BREQ0#, CPURST#, DEFER#, HTRDY#, RS[2:0]# HCLKP, HCLKN HDVREF[2:0], HDRCOMP, HDSWING
DDR Interface Signal Groups (l) DDR SSTL_2 I/O SDQ_A[63:0], SDQ_B[63:0], SDQS_A[7:0], SDQS_B[7:0] SDM_A[7:0], SDM_B[7:0], SCMDCLK_A[5:0], SCMDCLK_B[5:0], SCMDCLK_A[5:0]#, SCMDCLK_B[5:0]#, SMAA_A[12:0], SMAA_B[12:0], SMAB_A[5:1], SMAB_B[5:1], SBA_A[1:0], SBA_B[1:0], SRAS_A#, SRAS_B#, SCAS_A#, SCAS_B#, SWE_A#, SWE_B#, SCS_A[3:0]#, SCS_B[3:0]#, SCKE_A[3:0], SCKE_B[3:0] SMXRCOMP, SMYRCOMP SMXRCOMPVOL, SMXRCOMPVOH, SMYRCOMPVOL, SMYRCOMPVOH, SMVREF_A, SMVREF_B
(m)
DDR SSTL_2 Output
(v) (n)
DDR RCOMP DDR Miscellaneous2
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Electrical Characteristics
Table 36. Signal Groups (Sheet 2 of 2)
Signal Group Signal Type Signals Notes1
DAC Signal Groups (o) (p) (q) Display Output Display Analog Outputs Display Miscellaneous VSYNC, HSYNC RED, GREEN, BLUE, RED#, GREEN#, BLUE# REFSET
DVO Signal Groups (r) (s) DVOx Input DVOx Output DVOBC_CLKINT, DVOx_FLD/STL, DVOBC_INTR# DVOx_CLK, DVOx_CLK#, DVOx_D[11:0], DVOx_HSYNC, DVOx_VSYNC, DVOx_BLANK#
Reset and Miscellaneous Signal Groups (t) (o) (w) (x) 2.6 V Miscellaneous Input (3.3 V tolerant) LVTTL 3.3 V Miscellaneous I/O FSB Select Input Clocks LVTTL RSTIN#, PWROK, EXTTS# DDCA_CLK, DDCA_DATA BSEL[0:1] GCLKIN, DREFCLK
NOTES: 1. For details on BSEL[1:0] pin electrical requirements, see the Intel(R) 865G/865GV/865PE/865P Chipset Platform Design Guide. 2. For additional details on SMXRCOMP, SMYRCOMP, SMXRCOMPVOL, SMXRCOMPVOH, SMYRCOMPVOL, SMYRCOMPVOH pin electrical requirements, see the Intel(R) 865G/865GV/865PE/865P Chipset Platform Design Guide.
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6.5
DC Parameters
All DC operating conditions are specified at the pin unless otherwise specified.
Table 37. DC Operating Characteristics (Sheet 1 of 2)
Signal Name I/O Buffer Supply Voltage VCC VCC_AGP VCCA_AGP VTT (Intel(R) Pentium(R) 4 processor with 512-KB L2 cache on 0.13 micron process) VTT (Intel(R) Pentium(R) 4 processor on 90 nm process VCC_DDR VCCA_DDR VCC_DAC VCCA_DAC VCCA_DPLL VCCA_FSB Reference Voltages GVREF (2.0) AGP 2.0 Reference Voltage 1/2 * VCC_AGP_min - 2% 0.2333 * VCC_AGP_min - 0.01 0.5333 * VCC_AGP_min - 0.05 0.343 0.784 0.343 0.784 (VTT_min + VccCPU_min)/2 1/2 * VCC_AGP 1/2 * VCC_AGP_max + 2% 0.2333 * VCC_AGP_max + 0.01 0.5333 * VCC_AGP_max + 0.05 0.357 0.816 0.357 0.816 (VTT_max + VccCPU_max)/2 V Core Voltage AGP I/O Voltage AGP Analog Supply Voltage 1.425 1.425 1.425 1.5 1.5 1.5 1.575 1.575 1.575 V V V Parameter Min Nom Max Unit
Host AGTL+ Termination Voltage
1.35
1.45
1.55
V
Host AGTL+ Termination Voltage DDR I/O Supply Voltage DDR Supply Voltage 3.3 V DAC Supply Voltage DAC Supply Voltage Display PLL Analog Voltage Host PLL Analog Voltage
1.14 2.5 1.425 3.135 1.425 1.425 1.425
1.225 2.6 1.5 3.3 1.5 1.5 1.5
1.31 2.7 1.575 3.465 1.6 1.575 1.575
V V V V V V V
GVREF (3.0)4
AGP 3.0 Reference Voltage
0.2333 * VCC_AGP
V
GVSWING (3.0)5 HI_VREF6,7 HI_SWING6,8 CI_VREF9,10 CI_SWING9,11 Vsh1
AGP 3.0 Swing Voltage Hub Interface Reference Voltage Hub Interface Compensation Reference Voltage CSA Interface Reference Voltage CSA Interface Compensation Reference Voltage GMCH VTT/processor Shared Voltage
0.5333 * VCC_AGP 0.35 0.8 0.35 0.8 (VTT + VccCPU)/2
V V V V V V
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Electrical Characteristics
Table 37. DC Operating Characteristics (Sheet 2 of 2)
Signal Name HDVREF2 HDSWING/ HASWING SMXRCOMPVOL3/ SMYRCOMPVOL SMXRCOMPVOH3/ SMYRCOMPVOH SMVREF Parameter Host Reference Voltage Host Compensation Reference Voltage DDR RCOMP VOL DDR RCOMP VOH DDR Reference Voltage Min 0.63 x Vsh_min - 2% 1/4 x VTT_min - 2% VCC_DDR_min * (1/4.112) - 2% VCC_DDR_min * (3.112/4.112) - 2% 0.49 x VCC_DDR_min Nom 0.63 x Vsh 1/4 x VTT VCC_DDR * (1/4.112) VCC_DDR * (3.112/4.112) 0.5 x VCC_DDR Max 0.63 x Vsh_max + 2% 1/4 x VTT_max + 2% VCC_DDR_max * (1/4.112) + 2% VCC_DDR_max * (3.112/4.112) + 2% 0.51 x VCC_DDR_max Unit V V V V V
NOTES: 1. Refer to the Intel(R) Pentium(R) 4 Processor with 512-KB L2 Cache on 0.13 Micron Process Datasheet VCC values used to calculate Vsh. For values pertaining to the Pentium 4 processor on 90 nm process, contact your Intel field representative. 2. HDVREF is generically referred to as GTLREF throughout the rest of this chapter. 3. SMXRCOMPVOL/SMYRCOMPVOL and SMXRCOMPVOH/SMYRCOMPVOH have maximum input leakage current of 1 mA. 4. Measured at receiver pad. 5. Standard 50 load to ground. 6. HI_REF and HI_SWING are derived from VCC (nominal VCC = 1.5 V) that is the nominal core voltage for the GMCH. Voltage supply tolerance for a particular interface driver voltage must be within a 5% range of nominal. 7. Nominal value of HI_REF is 0.350 V. The specification is at nominal VCC. Note that HI_REF varies linearly with VCC; thus, VCC variation ( 5%) must be accounted for in the HI_REF specification in addition to the 2% variation of HI_REF in the table. 8. Nominal value of HI_SWING is 0.800 V. The specification is at nominal VCC. Note that HI_SWING varies linearly with VCC; thus, VCC variation ( 5%) must be accounted for in the HI_SWING specification in addition to the 2% variation of HI_SWING in the table. 9. CI_REF and CI_SWING are derived from VCC (nominal VCC = 1.5 V) that is the nominal core voltage for the GMCH. Voltage supply tolerance for a particular interface driver voltage must be within a 5% range of nominal. 10.Nominal value of CI_VREF is 0.350 V. The specification is at nominal VCC. Note that CI_VREF varies linearly with VCC; thus, VCC variation ( 5%) must be accounted for in the CI_VREF specification in addition to the 2% variation of CI_REF in the table. 11. Nominal value of CI_SWING is 0.800 V. The specification is at nominal VCC. Note that CI_SWING varies linearly with VCC; thus, VCC variation ( 5%) must be accounted for in the CI_SWING specification in addition to the 2% variation of CI_SWING in the table. 12.For AC noise components >20 MHz, the maximum allowable noise component at the GMCH is 180 mV at VCC_nom, +180/-105 mV at VCC_min, and +105/-180 mV at VCC_max. For AC noise components <20 MHz, the sum of the DC voltage and AC noise component must be within the specified DC minimum/ maximum operating range.
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Table 38. DC Characteristics (Sheet 1 of 3)
Symbol Signal Group Parameter Min Nom Max Unit Notes
1.5 V AGP 2.0 (1.5 V signaling) and DVO Interface6
VIL_AGP VIH_AGP VOL_AGP VOH_AGP IOL_AGP IOH_AGP ILEAK_AGP CIN_AGP
(a,b,r) (a,b,r) (a,c,s) (a,c,s) (a,c,s) (a,c,s) (a,b,r) (a,b,r)
AGP/DVO Input Low Voltage AGP/DVO Input High Voltage AGP/DVO Output Low Voltage AGP/DVO Output High Voltage AGP/DVO Output Low Current AGP/DVO Output High Current AGP/DVO Input Leakage Current AGP/DVO Input Capacitance
Interface6
-0.5
AGP_VREF + 0.15
AGP_VREF - 0.15 VCC_AGP + 0.5 0.225
V V V V
1.275 6.65
mA mA
@ 0.1* VCC_AGP @ 0.85* VCC_AGP 0-4.7
25
A
4
pF
1.5 V AGP 3.0 (0.8 V signaling) and DVO
VIL_AGP VIH_AGP VOL_AGP VOH_AGP IOH_AGP ILEAK_AGP CIN_AGP
(a,b,r) (a,b,r) (a,c,s) (a,c,s) (a,c,s) (a,b,r) (a,b,r)
AGP/DVO Input Low Voltage AGP/DVO Input High Voltage AGP/DVO Output Low Voltage AGP/DVO Output High Voltage AGP/DVO Output High Current AGP/DVO Input Leakage Current AGP/DVO Input Capacitance
-0.3
AGP_VREF + 0.10
AGP_VREF - 0.1 VCC_AGP 0.05
V V V V mA
A
Iout = 1500 A Standard 50 load to ground.
0.5333 * VCC_AGP_min - 0.05 14.54
0.5333 * VCC_AGP
0.5333 * VCC_AGP_ max + 0.05 17.78
25
1
2.5
pF
FC=1 MHz
1.5 V Hub Interface7
VIL_HI VIH_HI VOL_HI VOH_HI ILEAK_HI CIN_HI
(e) (e) (e) (e) (e) (e)
Hub Interface Input Low Voltage Hub Interface Input High Voltage Hub Interface Output Low Voltage Hub Interface Output High Voltage Hub Interface Input Leakage Current Hub Interface Input Capacitance
-0.3
HI_VREF + 0.1
HI_VREF - 0.1 1.2 0.05
V V V V
A
IOL= 1 mA IOUT = 0.8/RTT, RTT = 60
0.6
1.2
50
5
pF
FC=1 MHz
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Electrical Characteristics
Table 38. DC Characteristics (Sheet 2 of 3)
Symbol Signal Group Parameter Min Nom Max Unit Notes
1.5 V CSA Interface8
VIL_CI VIH_CI VOL_CI VOH_CI ILEAK_CI CIN_CI
(e) (e) (e) (e) (e) (e)
CSA Interface Input Low Voltage CSA Interface Input High Voltage CSA Interface Output Low Voltage CSA Interface Output High Voltage CSA Interface Input Leakage Current CSA Interface Input Capacitance
-0.3
CI_VREF + 0.1
CI_VREF - 0.1 1.2 0.05
V V V V
A
IOL= 1 mA IOUT = 0.8/RTT, RTT = 60
0.6
1.2
50
5
pF
FC=1 MHz
VTT DC Characteristics
VIL_AGTL+ VIH_AGTL+ VOL_AGTL+ VOH_AGTL+ IOL_AGTL+ ILEAK_AGTL+ CPAD_AGTL+
(g,h) (g,h) (g,i) (g,i) (g,i) (g,h) (g,h)
Host AGTL+ Input Low Voltage Host AGTL+ Input High Voltage Host AGTL+ Output Low Voltage Host AGTL+ Output High Voltage Host AGTL+ Output Low Current Host AGTL+ Input Leakage Current Host AGTL+ Input Capacitance 1 (Vsh-0.1) * 0.95 HDVREF + (0.04*Vsh) 1/4* Vsh
HDVREF -(0.04*Vsh)
V V V
Vsh 0.75 * Vshmax / Rttmin
25
V mA
A
Rttmin=57 VOL3.3
pF
2.6 V DDR System Memory
VIL_DDR(DC) VIH_DDR(DC) VIL_DDR(AC) VIH_DDR(AC) VOL_DDR
(l) (l) (l) (l) (l,m,v)
DDR Input Low Voltage DDR Input High Voltage DDR Input Low Voltage DDR Input High Voltage DDR Output Low Voltage DDR Output High Voltage DDR Output Low Current DDR Output High Current DDR RCOMP Output Low Current DDR RCOMP Output High Current Input Leakage Current DDR Input /Output Pin Capacitance
-0.1 * VCC_DDR
SMVREF + 0.15
SMVREF - 0.15 VCC_DDR SMVREF- 0.31 VCC_DDR 0.600
V V V V V With 50 termination to DDR VTT. With 50 termination to DDR VTT. With 50 termination to DDR VTT. With 50 termination to DDR VTT.
-0.1 * VCC_DDR
SMVREF + 0.31
VOH_DDR
(l,m,v)
VCC_DDR - 0.600
V
IOL_DDR
(l,m)
25
mA
IOH_DDR IOL_DDR RCOMP IOH_DDR RCOMP ILeak_DDR CIN_DDR
(l,m) (v) (v) (l) (l)
-25
50
mA mA mA
15 A
-50
5.5
pF
FC=1 MHz
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Electrical Characteristics
Table 38. DC Characteristics (Sheet 3 of 3)
Symbol Signal Group Parameter Min Nom Max Unit Notes
2.6 V Miscellaneous Signals (3.3 V tolerant)
VIL VIH ILEAK CIN
(t) (t) (t) (t)
2.6 V Input Low Voltage 2.6 V Input High Voltage 2.6 V Input Leakage Current 2.6 V Input Capacitance VCC_DDR - 0.4
0.4 VCC_DAC 50 5.5
V V
A
pF
3.3 V Miscellaneous Signals
VIL VIH VOL VOH IOL IOH ILEAK CIN
(o) (o) (o) (o) (o) (o) (o) (o)
3.3V Input Low Voltage 3.3 V Input High Voltage 3.3 V Output Low Voltage 3.3 V Output High Voltage 3.3 V Output Low Current 3.3 V Output High Current 3.3 V Input Leakage Current 3.3 V Input Capacitance -50 VCC_DAC - 0.2 VCC_DAC - 0.4
0.4 VCC_DAC 0.2
V V V V
50
mA mA
@VOL max @VOH min
50 5.5
A
pF
FSB Select Signals
VIL VIH
Clocks
(w) (w)
Input Low Voltage Input High Voltage 0.8
0.4
V V
VIL VIH ILEAK CIN VCROSS(abs) VCROSS(rel)
(x) (x) (x) (x) (j) (j)
Input Low Voltage Input High Voltage Input Leakage Current Input Capacitance Absolute Crossing Voltage Relative Crossing Voltage 0.250 0.250 + 0.5 (VHavg - 0.700) NA VCC_DDR - 0.4
0.4 VCC_DAC 100 5.5 0.550 0.550 + 0.5(VHavg - 0.700)
V V
A
1
pF V V 2,3 3,4,5
NOTES: 1. Absolute max overshoot = 4.5 V 2. Crossing voltage is defined as the instantaneous voltage value when the rising edge of HCLKP equals the falling edge of HCLKN. 3. The crossing point must meet the absolute and relative crossing point specifications simultaneously. 4. VHavg is the statistical average of the VH measured by the oscilloscope. 5. VHavg can be measured directly using "Vtop" on Agilent* oscilloscopes and "High" on Tektronix oscilloscopes. 6. Maximum leakage current specification for the GVREF pin is 65 uA. The Maximum leakage current specification for the GVSWING pin is 50 A. Refer to Intel(R) 865G/865GV/865PE/865P Chipset Platform Design Guide for the resistor divider circuit details that take this specification into account. 7. Maximum leakage current specification for HI_VREF and HI_SWING pins is 50 A. Refer to 865G/865GV/ 865PE/865P Chipset Platform Design Guide for the resistor divider circuit details that take this specification into account. 8. Maximum leakage current specification for CI_VREF and CI_SWING pins is 50 A. Refer to 865G/865GV/ 865PE Chipset Platform Design Guide for the resistor divider circuit details that take this specification into account.
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Electrical Characteristics
6.6
DAC
The GMCH DAC (digital-to-analog converter) consists of three, identical 8-bit DACs to provide red, green, and blue color components.
6.6.1
DAC DC Characteristics
Table 39. DAC DC Characteristics
Parameter DAC Resolution Max Luminance (full-scale) Min Luminance LSB Current Integral Linearity (INL) Differential Linearity (DNL) Video channel-channel voltage amplitude mismatch Monotonicity Guaranteed -1.0 -1.0 Min 8 0.665 0.700 0.000 73.2 +1.0 +1.0 6 0.770 Typical Max Units Bits V V A LSB LSB % 1 1, 2, 4, white video level voltage 1, 3, 4, black video level voltage 4, 5 1 1 6 Notes
NOTES: 1. Measured at each R,G,B termination according to the VESA Test Procedure - Evaluation of Analog Display Graphics Subsystems Proposal (Version 1, Draft 4, December 1, 2000). 2. Max steady-state amplitude. 3. Min steady-state amplitude. 4. Defined for a double 75 termination. 5. Set by external reference resistor value. 6. Max full-scale voltage difference among R,G,B outputs (percentage of steady-state full-scale voltage).
6.6.2
DAC Reference and Output Specifications
Table 40. DAC Reference and Output Specifications
Parameter Reference resistor Min 124 Typical 127 Max 130 Units Notes1 1% tolerance, 1/16
NOTE: 1. Refer to the Intel(R) 865G/865GV/865PE/865P Chipset Platform Design Guide for details on video filter implementation.
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6.6.3
DAC AC Characteristics
Table 41. DAC AC Characteristics
Parameter Pixel Clock Frequency R,G,B Video Rise Time 0.57 Min Typical Max 350 1.43 Units MHz ns (10-90% of black-to-white transition, @ 350 MHz pixel clock) (90-10% of white-to-black transition, @ 350 MHz pixel clock) @ 350 MHz pixel clock @ 350 MHz pixel clock Full-scale voltage step of 0.7 V Notes
R,G,B Video Fall Time Settling Time Video channel-tochannel output skew Overshoot/ Undershoot Noise Injection Ratio VCCA_DAC DC to 10 MHz 10 MHz to Pixel Clock Frequency
0.57
1.43 0.86 0.714
ns ns ns V % V V
-0.084
+0.084 0.5
VCCA_DAC - 0.3% VCCA_DAC - 0.9%
VCCA_DAC VCCA_DAC
VCCA_DAC + 0.3% VCCA_DAC + 0.9%
(1) DAC Supply Voltage
NOTES: 1. Any deviation from this specification should be validated. Refer to the Intel(R) 865G/865GV/865PE/865P Chipset Platform Design Guide for the VCCA_DAC filter circuit implementation.
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Ballout and Package Information
Ballout and Package Information
This chapter provides the GMCH ballout and package information.
7
7.1
GMCH Ballout
The ballout footprint is shown in Figure 16 and Figure 17. These figures represent the ballout arranged by ball number. Table 42 provides the ballout arranged alphabetically by signal name. Note: The following notes apply to the ballout. 1. For the multiplexed AGP and DVO signals, only the AGP signal names are listed in this chapter. Refer to Section 2.5.7 for the DVO-to-AGP signal mapping. 2. For AGP signals, only the AGP 3.0 signal name is listed. For the corresponding AGP 2.0 signal name, refer to Chapter 2. 3. NC = No Connect. 4. RSVD = These reserved balls should not be connected and should be allowed to float. 5. Shaded cells in Figure 16 and Figure 17 do not have a ball.
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Ballout and Package Information
Figure 16. Intel(R) 82865G GMCH Ballout Diagram (Top View--Left Side)
35 AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A
NC VSS VSS VSS VSS VSS VCC_DDR VSS VSS VSS VSS VSS RSVD VSS NC RSVD SDQ_A31 SMAB_A2 SDQ_A27 VSS SCMD CLK_A0 VSS SCMD CLK_A0# SMAA_B1 SCMDCLK_ B3 VSS SCMD CLK_B0# VSS SDQ_B32 VSS SDQ_B34 VSS SDQ_B40 VSS SDQ_B41 VSS SDQS_B5 VSS SDQ_B49 VSS SCMD CLK_B5# VSS SDQ_B51 SDQ_B56 VSS SDQ_B50 VSS SDM_B6 VSS SDQ_B48 VSS SCS_B1# VSS SDQ_B45 VSS SDQ_B35 VSS SDQ_B37 VSS SDQS_B4 VSS SCMD CLK_B3# SCMD CLK_B0 SMAA_ B10 VSS
34
33
NC
32
VSS
31
VCC_DDR
30
29
VSS
28
27
VSS
26
25
VSS
24
23
VSS SDQS_A2 SMAA_A11 VSS SMAA_B8 SDQ_B19
22
21
VCC_DDR
20
VSS SCKE_A3 VSS SCKE_A2 SCKE_A0 VSS SMAA_B12 VSS
19
18
SDQ_A26 SMAB_A3 SMAB_A4 VSS SMAA_A3 SDQ_A30
SDM_A3 VSS SDQS_A3
SDQ_A25 SDQ_A24 SDQ_A23 SMAA_A8 SDQ_A22 SMAA_A9 SDQ_A29 VSS VSS SDQ_A28 SDQ_A19 VSS VSS SMAB_A5 SMAA_A7 VSS VSS SDM_A2
SDQ_A16 VSS SDQ_A17 SDQ_A21 VSS SMAA_B9 VSS
SDQ_A20 SMAA_A12 VSS SMAA_B11 SDQ_B21
SDQ_A11 SCKE_A1 VSS SDQ_B20 SCKE_B0
SDQ_A14 VSS SDQ_A15 SDQ_A10 VSS SDQ_B15 VSS
VCCA_DDR SMAB_A1 SMAA_A1 SCMD CLK_A3# SMAA_A0 SBA_A1 SCMD CLK_A3 SMAA_ A10 VSS
SMAA_A4 SMAB_B3 SMAA_A6 SMAB_B4 SMAA_A5 SMAA_B6 SDQ_A18 SMAA_A2 VSS SDM_B3 SMAA_B4 VSS SDQ_B24 VSS SDQ_B22 VSS SMAA_B5 VSS VSS VSS VSS VSS SMAA_B3
SDQ_B29 SDQ_B28 SDQS_B3 SDQ_B25 SDQ_B26 VSS
SDQ_A32 SDQ_A36 VSS SDQ_A34 VSS SMAA_B0 SDM_A4 SDQ_B36
SDQ_A33 SDQ_A37 SDQS_A4 SDQ_A38 SDQ_A39 SDQ_A40 SWE_A# SCS_A0# SCAS_A# SCS_A3# SDQS_A5 VSS SBA_A0 VSS SAS_A# VSS SMYRCO MP VSS SDM_A5 VSS
SDQ_B18 NC SMAB_B5
VSS VSS SDQ_B23
SDQS_B2 SMAA_B7 SDM_B2
VSS VSS SDQ_B17
SCKE_B2 SCKE_B1 SDQ_B16
VSS VSS SCKE_B3
SDQ_B31 SDQ_B27 SMAB_B1
SDQ_A35 SDQ_A44 VSS SDM_B4
SMAA_B2 SMAB_B2 SDQ_B30 SDQ_B33 VSS VCCA_ DDR VSS VCCA_ DDR VCCA_ DDR
SDQ_A45 SDQ_A41 VSS SDQ_B44
SDQ_B39 SDQ_B38 SBA_B1 VSS VSS SBA_B0 VCC VCC VCC VCC VCC VCC VCC VSS VSS VCC VCC VSS VCC VSS VCC
SCS_A2# SCS_A1# VSS SCAS_B#
SWE_B# SRAS_B# SCS_B3# VSS VSS SCS_B2#
SDQ_A42 SDQ_A43 VSS SDM_B5
SDQ_A46 SDQ_A47 SDQ_A48 VSS
SDQ_B42 SCS_B0# SDQ_B46 VSS VSS SDQ_B43 NC SDQ_B54
SDQ_A49 SDQ_A52 VSS SCMD CLK_A5# VSS SDQS_A6 SDQ_B52 SCMDC LK_A5 SCMD CLK_B5 NC VSS
SMYRCOM SMYRCO VCC_DDR PVOH MPVOL SDQ_A53 SCMD CLK_A2# SDM_A6 VSS SCMD CLK_A2 VSS
SDQ_B47 SDQ_B53 VSS SCMD CLK_B2 VSS SDQS_B6 VSS HA21# HA25# VSS HA23# HA19# HA24# HADSTB1# VSS BNR# HA22# ADS# DBSY# VSS RS1# RS2# VSS HA30# VSS HA31# VSS NC HA3# VSS BPRI# VSS
SCMD SDQ_B60 CLK_B2# VSS VSS SDQ_B61 VSS VSS HA11# VSS HA26# HA15# VSS DRDY# HA16# VSS HDVREF HITM# VSS NC HD0# VSS HA5# HA8# HREQ1# HREQ2# VSS VSS VSS RS0# VSS HD1# HD5# VSS HD4# HD24# HD27# VSS HD7# HD2# VTT DEFER# HIT# HREQ4# PROCHOT# HDSTBP1# VSS VSS VSS HD16# VSS HD9# HD3# VSS HD6# VSS HD19# HD18# VSS HDSTBNB_0 HDSTBP0# HDSTBNB_1 HD28# HD21# VSS VSS VSS HD23# VSS HD8# HD15# VSS HD12#
SDQ_A54 SDQ_A55 SDQ_B55 SDQ_A50 VSS
SDQ_A51 SDQ_A60 VSS SDM_A7 SDM_B7 SDQS_A7 VSS HA28#
SDQ_A61 SDQ_A56 SDQ_A57 VSS
SDQS_B7 SDQ_B62 VSS HA29# SDQ_B57
SDQ_A62 SDQ_B59 SDQ_B63 SDQ_A63 SDQ_A59 SDQ_B58
VCC_DDR SMVREF_A SDQ_A58 VSS NC HA17# HA20# NC HA14# NC VSS
HA27# VSS HA18# HA7# VSS HA10# HA12# VCCA_FSB
HA13# HA4# HA9#
HA6# VSS HREQ3#
HLOCK# HDRCOMP VSS HD SWING NC VSS HTRDY# VSS BREQ0#
HADSTB0# HREQ0# VSS
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
198
Intel(R) 82865G/82865GV GMCH Datasheet
Ballout and Package Information
Figure 17. Intel(R) 82865G GMCH Ballout Diagram (Top View--Right Side)
17 16
VSS SCMD CLK_A1 SCMD CLK_A1# VSS SDQ_B11 SDQ_B10 SDM_A1 VSS SCMD CLK_A4 SCMD CLK_A4# VSS SDQ_B14 VSS SCMD CLK_B1# SCMD CLK_B1 SDQ_B8 VSS VSS SDQ_B3 SDM_B1 SDQS_B0 SDQ_B1
15
VCC_DDR SDQS_A1 SDQ_A13 VSS SCMD CLK_B4# SCMD CLK_B4
14
13
VSS
12
11
VSS
10
9
VSS
8
7
VCC_DDR
6
5
4
3
NC VCC_DDR
2
1
RSVD
VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR HI4 CISTRF CISTRS HISTRF HI3 HI0 GAD3 GAD2 HI7 RSTIN# VSS HISTRS VSS CI_VREF VSS HI_RCOMP VSS GDEVSEL VSS GAD17 VSS
AR AP
SDQ_A8 VSS SDQ_A9 SDQ_A12 VSS SDQ_B13 VSS VSS VSS PWROK
SDQ_A7 SDQ_A3 VSS SDQ_B9 SDQ_B12
SDM_A0 VSS SDQ_A2 SDQ_A6 VSS NC VSS
SDQ_A1 SDQS_A0 VSS SDQ_B2 SDQ_B6
SDQ_A0 VSS SDQ_A4 SDQ_A5 VSS SDQ_B0 VSS
SMVREF_B
EXTTS#
VCC_DDR VCC_DDR VCC_DDR VCC_DDR CI0
NC VCC_DDR NC VCC_DDR VSS
SMXRCOM VCC_DDR PVOH VSS SMXRCOM PVOL SMX RCOMP VSS CI9 RSVD VSS VSS CI6 VCC_DDR SDQ_B4 VSS RSVD
AN AM AL AK
VCC_DDR HI5 VSS HI10 VSS HI1 VSS HI_SWING VSS GVSWING VSS GC#/BE2 VSS GAD22 VSS GAD23 VSS GSBA2# VSS GST0 VSS VCC_AGP VCC_AGP VCC_AGP DDCA_DATA HSYNC VSS VSS VSSA_DAC VSS VCCA_FSB VCCA_DPLL
VCC_DDR HI6 HI2 HI8 HI9 CI_RCOMP CI_SWING HI_VREF GVREF GRCOMP/ DVOBRCOMP GPAR/ ADD_DETECT GAD16 GAD18 GAD19 GAD21 GC#/BE3 GAD24 GAD27 GAD28 GST2 GAD31 VCC_AGP VCC_AGP VCC_AGP VSS VCC_DAC DDCA_CLK VSYNC REFSET VCCA_DAC NC
VSS
AJ AH
CI1 CI7 CI3
VSS CI10 VSS GAD0
SDQS_B1 NC VSS
SDQ_B7 SDQ_B5 VSS
SDM_B0 VSS VSS CI2 GAD1 GAD6 GAD12
TESTIN#
VCCA_ AGP
AG AF
VSS VSS CI5 VSS GAD4 VSS GAD11 VSS GSBA5# VSS GRBF VCC VCC VCC VCC
CI8 VSS GAD5 VSS GAD8 VSS GAD14 VSS GSBA4# VSS GWBF VSS VCC VCC VCC VCC VCC VCC VSS HD46# VSS CPURST# HD62# VSS HD63# VTT VTT VTT HCLKN HCLKP VCC GGNT VCC VCC VCC BLUE VSS GSBA1# VSS GSBA7# VSS GAD15 VSS GC#/BE0 VSS GAD7 VSS CI4
VSS
AE AD
VSS
GADSTBF0 GADSTBS0 VSS GAD9 VSS GAD13 VSS GFRAME VSS GSBA0# VSS GREQ VSS VCC VCC VCC GREEN BLUE# GTRDY GAD10 GAD20 GC#/BE1
VSS
AC AB
VSS VCC_AGP
AA Y W V U
VCC VSS VSS VCC VCC
VCC VCC VCC VCC VCC
VCCA_AGP GSTOP GIRDY GSBSTBF GSBSTBS VCC VCC VCC VCC
GADSTBS1 GADSTBF1 GSBA6# GAD26 GSBA3# GAD29 GST1 DBI_LO VSS GAD25 VSS GAD30 VSS DBI_HI
VSS VSS
T R P
VSS
N M
DINV1# HD31# HD20#
HD33# VSS VSS VSS HD22#
HD41# HD38# HD32#
DINV2# VSS VSS VSS HD29#
BSEL0 HD43# HD34#
BSEL1 VSS VSS VSS HD39#
VCC VSS HD44#
VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VSS GREEN# VSS GCLKIN DREFCLK RED RED# VTT VTT VTT
VCC_AGP
L K
VSS HD45# HD40#
VCC VSS HDSTBP2# HDSTBN2# HD47# VSS HD60# HD61#
VCC_AGP
J H
VCC_DAC VSS VSS VSS NC
G F E D C B A
HD17# HD30# VSS DINV0# HD13#
VSS HD14# HD11# VSS HD10#
HD25# HD26# VSS DINV3# HD52#
VSS HD49# HD53# VSS HD50#
HD35# HD37# VSS HD54# HD48#
VSS HDSTBN3# HDSTBP3# VSS HD51#
HD36# HD42# VSS HD57# HD55#
VSS HD58# HD56# VSS HD59#
VTT VTT VTT VTT
VSS 17 16
VTT 15 14
VSS 13 12
VSS 11 10
VSS 9 8
VSS 7
VTT 6
VTT 5
VTT 4
NC 3 2 1
Intel(R) 82865G/82865GV GMCH Datasheet
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Intel(R) 82865G/82865GV GMCH Datasheet
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Table 42. Intel(R) 82865G Ball List by Signal Name
Signal Name ADS# BLUE BLUE# BNR# BPRI# BREQ0# BSEL0 BSEL1 CI_RCOMP CI_SWING CI_VREF CI0 CI1 CI10 CI2 CI3 CI4 CI5 CI6 CI7 CI8 CI9 CISTRF CISTRS CPURST# DBI_HI DBI_LO DBSY# DDCA_CLK DDCA_DATA DEFER# DINV0# DINV1# DINV2# DINV3# DRDY# DREFCLK EXTTS# GAD0 GAD1 Ball # F27 H7 G6 B28 B26 B24 L13 L12 AG2 AF2 AF4 AK7 AH7 AG6 AD11 AF7 AD7 AC10 AF8 AG7 AE9 AH9 AJ6 AJ5 E8 M4 M5 E27 F2 H3 L21 C17 L17 L14 C15 G24 G4 AP8 AE6 AC11
Table 42. Intel(R) 82865G Ball List by Signal Name
Signal Name GAD2 GAD3 GAD4 GAD5 GAD6 GAD7 GAD8 GAD9 GAD10 GAD11 GAD12 GAD13 GAD14 GAD15 GAD16 GAD17 GAD18 GAD19 GAD20 GAD21 GAD22 GAD23 GAD24 GAD25 GAD26 GAD27 GAD28 GAD29 GAD30 GAD31 GADSTBF0 GADSTBF1 GADSTBS0 GADSTBS1 GC#/BE0 GC#/BE1 GC#/BE2 GC#/BE3 GCLKIN GDEVSEL Ball # AD5 AE5 AA10 AC9 AB11 AB7 AA9 AA6 AA5 W10 AA11 W6 W9 V7 AA2 Y4 Y2 W2 Y5 V2 W3 U3 T2 T4 T5 R2 P2 P5 P4 M2 AC6 V4 AC5 V5 Y7 W5 AA3 U2 H4 AB4
Table 42. Intel(R) 82865G Ball List by Signal Name
Signal Name GFRAME GGNT GIRDY GPAR/ADD_DETECT GRBF GRCOMP/ DVOBRCOMP GREEN GREEN# GREQ GSBA0# GSBA1# GSBA2# GSBA3# GSBA4# GSBA5# GSBA6# GSBA7# GSBSTBF GSBSTBS GST0 GST1 GST2 GSTOP GTRDY GVREF GVSWING GWBF HA3# HA4# HA5# HA6# HA7# HA8# HA9# HA10# HA11# HA12# HA13# HA14# Ball # U6 M7 V11 AB2 R10 AC2 H6 G5 N6 R6 P7 R3 R5 U9 U10 U5 T7 U11 T11 N3 N5 N2 W11 AB5 AD2 AC3 R9 D26 D30 L23 E29 B32 K23 C30 C31 J25 B31 E30 B33
Intel(R) 82865G/82865GV GMCH Datasheet
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Table 42. Intel(R) 82865G Ball List by Signal Name
Signal Name HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31# HADSTB0# HADSTB1# HCLKN HCLKP HD0# HD1# HD2# HD3# HD4# HD5# HD6# HD7# HD8# HD9# HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# Ball # J24 F25 D34 C32 F28 C34 J27 G27 F29 E28 H27 K24 E32 F31 G30 J26 G26 B30 D28 C7 B7 B23 E22 B21 D20 B22 D22 B20 C21 E18 E20 B16 D16 B18 B17 E16 D18 G20 F17 E19
Table 42. Intel(R) 82865G Ball List by Signal Name
Signal Name HD19# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49# HD50# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# Ball # F19 J17 L18 G16 G18 F21 F15 E15 E21 J19 G14 E17 K17 J15 L16 J13 F13 F11 E13 K15 G12 G10 L15 E11 K13 J11 H10 G8 E9 B13 E14 B14 B12 B15 D14 C13 B11 D10 C11 E10
Table 42. Intel(R) 82865G Ball List by Signal Name
Signal Name HD59# HD60# HD61# HD62# HD63# HDRCOMP HDSTBN0# HDSTBN1# HDSTBN2# HDSTBN3# HDSTBP0# HDSTBP1# HDSTBP2# HDSTBP3# HDSWING HDVREF HI_RCOMP HI_SWING HI_VREF HI0 HI1 HI2 HI3 HI4 HI5 HI6 HI7 HI8 HI9 HI10 HISTRF HISTRS HIT# HITM# HLOCK# HREQ0# HREQ1# HREQ2# HREQ3# HREQ4# Ball # B10 C9 B9 D8 B8 E24 C19 K19 F9 E12 B19 L19 G9 D12 C25 F23 AD4 AE3 AE2 AF5 AG3 AK2 AG5 AK5 AL3 AL2 AL4 AJ2 AH2 AJ3 AH5 AH4 K21 E23 E25 B29 J23 L22 C29 J21
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Table 42. Intel(R) 82865G Ball List by Signal Name
Signal Name HSYNC HTRDY# NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC PROCHOT# PWROK RED RED# REFSET RS0# RS1# RS2# RSTIN# RSVD RSVD RSVD RSVD RSVD TESTIN# SBA_A0 SBA_A1 SBA_B0 Ball # G3 D24 A3 A33 A35 AF13 AF23 AJ12 AN1 AP2 AR3 AR33 AR35 B2 B25 B34 C1 C23 C35 E26 M31 R25 L20 AE14 F4 E4 D2 G22 C27 B27 AK4 AJ8 AR1 AP34 AG9 AN35 AG10 AE33 AH34 Y25
Table 42. Intel(R) 82865G Ball List by Signal Name
Signal Name SBA_B1 SCAS_A# SCAS_B# SCKE_A0 SCKE_A1 SCKE_A2 SCKE_A3 SCKE_B0 SCKE_B1 SCKE_B2 SCKE_B3 SCMDCLK_A0 SCMDCLK_A0# SCMDCLK_A1 SCMDCLK_A1# SCMDCLK_A2 SCMDCLK_A2# SCMDCLK_A3 SCMDCLK_A3# SCMDCLK_A4 SCMDCLK_A4# SCMDCLK_A5 SCMDCLK_A5# SCMDCLK_B0 SCMDCLK_B0# SCMDCLK_B1 SCMDCLK_B1# SCMDCLK_B2 SCMDCLK_B2# SCMDCLK_B3 SCMDCLK_B3# SCMDCLK_B4 SCMDCLK_B4# SCMDCLK_B5 SCMDCLK_B5# SCS_A0# SCS_A1# SCS_A2# SCS_A3# SCS_B0# Ball # AA25 Y34 W31 AL20 AN19 AM20 AP20 AK19 AF19 AG19 AE18 AK32 AK31 AP17 AN17 N33 N34 AK33 AK34 AM16 AL16 P31 P32 AG29 AG30 AF17
AG17
Table 42. Intel(R) 82865G Ball List by Signal Name
Signal Name SCS_B1# SCS_B2# SCS_B3# SDM_A0 SDM_A1 SDM_A2 SDM_A3 SDM_A4 SDM_A5 SDM_A6 SDM_A7 SDM_B0 SDM_B1 SDM_B2 SDM_B3 SDM_B4 SDM_B5 SDM_B6 SDM_B7 SDQ_A_17 SDQ_A0 SDQ_A1 SDQ_A2 SDQ_A3 SDQ_A4 SDQ_A5 SDQ_A6 SDQ_A7 SDQ_A8 SDQ_A9 SDQ_A10 SDQ_A11 SDQ_A12 SDQ_A13 SDQ_A14 SDQ_A15 SDQ_A16 SDQ_A18 SDQ_A19 SDQ_A20 Ball # T29 V25 W25 AP12 AP16 AM24 AP30 AF31 W33 M34 H32 AG11 AG15 AE21 AJ28 AC31 U31 M29 J31 AM22 AP10 AP11 AM12 AN13 AM10 AL10 AL12 AP13 AP14 AM14 AL18 AP19 AL14 AN15 AP18 AM18 AP22 AL24 AN27 AP21
N27 N26 AJ30 AH29 AK15 AL15 N31 N30 AA34 Y31 Y32 W34 U26
Intel(R) 82865G/82865GV GMCH Datasheet
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Table 42. Intel(R) 82865G Ball List by Signal Name
Signal Name SDQ_A21 SDQ_A22 SDQ_A23 SDQ_A24 SDQ_A25 SDQ_A26 SDQ_A27 SDQ_A28 SDQ_A29 SDQ_A30 SDQ_A31 SDQ_A32 SDQ_A33 SDQ_A34 SDQ_A35 SDQ_A36 SDQ_A37 SDQ_A38 SDQ_A39 SDQ_A40 SDQ_A41 SDQ_A42 SDQ_A43 SDQ_A44 SDQ_A45 SDQ_A46 SDQ_A47 SDQ_A48 SDQ_A49 SDQ_A50 SDQ_A51 SDQ_A52 SDQ_A53 SDQ_A54 SDQ_A55 SDQ_A56 SDQ_A57 SDQ_A58 SDQ_A59 SDQ_A60 Ball # AL22 AP25 AP27 AP28 AP29 AP33 AM33 AM28 AN29 AM31 AN34 AH32 AG34 AF32 AD32 AH31 AG33 AE34 AD34 AC34 AB31 V32 V31 AD31 AB32 U34 U33 T34 T32 K34 K32 T31 P34 L34 L33 J33 H34 E33 F33 K31
Table 42. Intel(R) 82865G Ball List by Signal Name
Signal Name SDQ_A61 SDQ_A62 SDQ_A63 SDQ_B0 SDQ_B1 SDQ_B2 SDQ_B3 SDQ_B4 SDQ_B5 SDQ_B6 SDQ_B7 SDQ_B8 SDQ_B9 SDQ_B10 SDQ_B11 SDQ_B12 SDQ_B13 SDQ_B14 SDQ_B15 SDQ_B16 SDQ_B17 SDQ_B18 SDQ_B19 SDQ_B20 SDQ_B21 SDQ_B22 SDQ_B23 SDQ_B24 SDQ_B25 SDQ_B26 SDQ_B27 SDQ_B28 SDQ_B29 SDQ_B30 SDQ_B31 SDQ_B32 SDQ_B33 SDQ_B34 SDQ_B35 SDQ_B36 Ball # J34 G34 F34 AJ10 AE15 AL11 AE16 AL8 AF12 AK11 AG12 AE17 AL13 AK17 AL17 AK13 AJ14 AJ16 AJ18 AE19 AE20 AG23 AK23 AL19 AK21 AJ24 AE22 AK25 AH26 AG27 AF27 AJ26 AJ27
AD25
Table 42. Intel(R) 82865G Ball List by Signal Name
Signal Name SDQ_B37 SDQ_B38 SDQ_B39 SDQ_B40 SDQ_B41 SDQ_B42 SDQ_B43 SDQ_B44 SDQ_B45 SDQ_B46 SDQ_B47 SDQ_B48 SDQ_B49 SDQ_B50 SDQ_B51 SDQ_B52 SDQ_B53 SDQ_B54 SDQ_B55 SDQ_B56 SDQ_B57 SDQ_B58 SDQ_B59 SDQ_B60 SDQ_B61 SDQ_B62 SDQ_B63 SDQS_A0 SDQS_A1 SDQS_A2 SDQS_A3 SDQS_A4 SDQS_A5 SDQS_A6 SDQS_A7 SDQS_B0 SDQS_B1 SDQS_B2 SDQS_B3 SDQS_B4 Ball # AB29 AA26 AA27 AA30 W30 U27 T25 AA31 V29 U25 R27 P29 R30 K28 L30 R31 R26 P25 L32 K30 H29 F32 G33 N25 M25 J29 G32 AN11 AP15 AP23 AM30 AF34 V34 M32 H31 AF15 AG13 AG21 AH27 AD29
AF28 AE30 AC27 AC30 Y29 AE31
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Table 42. Intel(R) 82865G Ball List by Signal Name
Signal Name SDQS_B5 SDQS_B6 SDQS_B7 SMAA_A0 SMAA_A1 SMAA_A2 SMAA_A3 SMAA_A4 SMAA_A5 SMAA_A6 SMAA_A7 SMAA_A8 SMAA_A9 SMAA_A10 SMAA_A11 SMAA_A12 SMAA_B0 SMAA_B1 SMAA_B2 SMAA_B3 SMAA_B4 SMAA_B5 SMAA_B6 SMAA_B7 SMAA_B8 SMAA_B9 SMAA_B10 SMAA_B11 SMAA_B12 SMAB_A1 SMAB_A2 SMAB_A3 SMAB_A4 SMAB_A5 SMAB_B1 SMAB_B2 SMAB_B3 SMAB_B4 SMAB_B5 SMVREF_A Ball # U30 L27 J30 AJ34 AL33 AK29
AN31
Table 42. Intel(R) 82865G Ball List by Signal Name
Signal Name SMVREF_B SMXRCOMP SMXRCOMPVOH SMXRCOMPVOL SMYRCOMP SMYRCOMPVOH SMYRCOMPVOL SRAS_A# SRAS_B# SWE_A# SWE_B# VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Ball # AP9 AK9 AN9 AL9 AA33 R34 R33 AC33 W26 AB34 W27 J6 J7 J8 J9 K6 K7 K8 K9 L10 L11 L6 L7 L9 M10 M11 M8 M9 N10 N11 N9 P10 P11 R11 T16 T17 T18 T19 T20 U16
Table 42. Intel(R) 82865G Ball List by Signal Name
Signal Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_DAC VCC_DAC VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR Ball # U17 U20 V16 V18 V20 W16 W19 W20 Y16 Y17 Y18 Y19 Y20 J1 J2 J3 J4 J5 K2 K3 K4 K5 L1 L2 L3 L4 L5 Y1 G1 G2 AA35 AL6 AL7 AM1 AM2 AM3 AM5 AM6 AM7 AM8
AL30 AL26 AL28 AN25 AP26 AP24 AJ33 AN23 AN21
AG31
AJ31
AD27
AE24 AK27 AG25 AL25 AF21 AL23 AJ22 AF29 AL21 AJ20 AL34 AM34 AP32 AP31 AM26 AE27 AD26 AL29 AL27 AE23 E34
Intel(R) 82865G/82865GV GMCH Datasheet
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Ballout and Package Information
Table 42. Intel(R) 82865G Ball List by Signal Name
Signal Name VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCCA_AGP VCCA_AGP VCCA_DAC VCCA_DDR VCCA_DDR VCCA_DDR VCCA_DDR VCCA_DPLL VCCA_FSB VCCA_FSB VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # AN2 AN4 AN5 AN6 AN7 AN8 AP3 AP4 AP5 AP6 AP7
AR15 AR21
Table 42. Intel(R) 82865G Ball List by Signal Name
Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # AG22 AG24 AG26 AG28 AG32 AG35 AG4 AG8 AH10 AH12 AH14 AH16 AH18 AN30 AN32 AR11 AR13 AR16
AR20 AR23 AR25 AR27 AR29 AR32
Table 42. Intel(R) 82865G Ball List by Signal Name
Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # D15 D17 D19 K29 K33 L24 L25 L26 L31 L35 M26 M27 M28 M3 M30 M33 M6 N1 N32 N35 N4 P26 P27 P28 P3 P30 P33 P6 P8 P9 R1 R32 R4 T1 T10 A11 A13 A16 A20 A23
AR31 AR4 AR5 AR7 E35 R35 AG1 Y11 C2
AC26
AL35 AB25
AC25
AR9 C10 C12 C14 C16 C18 C20 C22 C24 C26 C28 C4 C8 D1 D11 D13
B3 A31 B4 AF24 AF25 AF3 AF30 AF33 AF6 AF9
AG14 AG16
AG18 AG20
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Table 42. Intel(R) 82865G Ball List by Signal Name
Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # A25 A27 A29 A32 A7 A9 AA1 AA32 AA4 AB10 AB26 AB27 AB28 AB3 AB30 AB33 AB6 AB8 AB9
AH20 AH22 AH24
Table 42. Intel(R) 82865G Ball List by Signal Name
Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # AK28 AK3 AK8 D21 D23 D25 D27 D29 D31 D33 D35 D9 E1 E3 F1 F10 F12 F14 F16 F18 F20 F22 F24 F26 F3 F5 F8 G28 G31 G35 H12 H14 H16 T26 T27 T28 T3 T30 T33 T35
Table 42. Intel(R) 82865G Ball List by Signal Name
Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # T6 T8 T9 U18 U19 U32 U4 V10 V17 V19 V26 V27 V28 V3 V30 V33 V6 V8 V9 W17 W18 W32 W4 Y10 Y26 AC1 AC32 AC35 AC4 AD10 AD28 AD3 AD30 AD33 AD6 AD8 AD9 AE1 AE10 AE11
AH3 AH30 AH33 AH6 AJ1 AJ32 AJ35 AJ4 AJ9 AK10 AK12 AK14 AK16 AK18 AK20 AK22 AK24 AK26
Intel(R) 82865G/82865GV GMCH Datasheet
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Table 42. Intel(R) 82865G Ball List by Signal Name
Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # AE12 AE13 AE25 AE26 AE32 AE35 AE4 AF11 AF14 AF16 AF18 AF20 AF22 AL1 AL32
AM11 AM13
Table 42. Intel(R) 82865G Ball List by Signal Name
Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball #
AN18
Table 42. Intel(R) 82865G Ball List by Signal Name
Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSA_DAC VSYNC VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT Ball # K18 K20 K22 K25 K27 Y27 Y28 Y3 Y30 Y33 Y35 Y6 Y8 Y9 D3 E2 A15 A21 A4 A5 A6 B5 B6 C5 C6 D5 D6 D7 E6 E7 F7
AN20
AN22 AN24
AN26 AN28 H18 H2 H20 H22 H24 H26 H30 H33 H5 H8 H9 J10 J12 J14 J16 J18 J20 J22 J28 J32 J35 K11 K12 K14 K16
AM15 AM17 AM19
AM21 AM23
AM25 AM27 AM29 AM35 AM9
AN10 AN12 AN14 AN16
208
Intel(R) 82865G/82865GV GMCH Datasheet
Ballout and Package Information
7.2
GMCH Package Information
The GMCH is in a 37.5 mm x 37.5 mm Flip Chip Ball Grid Array (FC-BGA) package with 932 solder balls. Figure 18 and Figure 19 show the package dimensions.
Figure 18. Intel(R) 82865G GMCH Package Dimensions (Top and Side Views)
Top View Detail A 17.9250 37.50 0.050 18.75 Detail A
18.75 17.9250
37.50 0.05
16.9500
Detail B
16.9500
Detail C
Side View 0.500 0.070 Substrate Die See Detail D 1.08 0.06 A 0.200 Detail A 0.203 C A B 0.6500 0.05 0.500 1.1500 0.05 1.00 Detail B 0.203 C A B Detail C Detail D 0.74 0.025 Underfill Epoxy Die Solder Bumps
1.5 0.05 0.57 0.1
0.100 0.025
3 x 0.07 0.57 0.1
Units = Millimeters
Pk 60 Sid T
Intel(R) 82865G/82865GV GMCH Datasheet
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Ballout and Package Information
Figure 19. Intel(R) 82865G GMCH Package Dimensions (Bottom View)
0.7668 Detail A 0.7668
1.0 mm Min.
Detail B Detail B Pin A1 Detail A BGA Land; 932 balls 0.600 (932 places) 0.57 0.1 0.203 0.7 0.05 0.7 0.05 0.071 0.63 0.025 0.7 0.05 0.47 0.04 L L
0.4529
ABS A
CS
0.57 0.1
Units = Millimeters
865_Pkg_Bottom_rev2
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Testability
In the GMCH, testability for Automated Test Equipment (ATE) board level testing has been implemented as an XOR chain. An XOR-tree is a chain of XOR gates, each with one input pin connected to it.
8
8.1
XOR Test Mode Initialization
XOR test mode can be entered by driving GSBA6#, GSBA7#, TESTIN#, PWROK low, and RSTIN# low, then driving PWROK high, then RSTIN# high. XOR test mode via TESTIN# does not require a clock. But toggling of HCLKP and HCLKN as shown in Figure 20 is required for deterministic XOR operation when in AGP 2.0 mode. If the component is in AGP 3.0 mode, GSBA6#, GSBA7#, and GC#/BE1 must be driven high.
Figure 20. XOR Toggling of HCLKP and HCLKN
1 ms PWROK TESTIN# GSBA6
GFRAME# RSTIN#
GCLKIN HCLKP HCLKN DREFCLK
Pin testing will not start until RSTIN# is deasserted. Figure 21 shows chains that are tested sequentially. Note that for the GMCH, sequential testing is not required. All chains can be tested in parallel for test time reduction.
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Figure 21. XOR Testing Chains Tested Sequentially
5 ms PWROK TESTIN# RSTIN# GSBA6 GFRAME# GCLKIN HCLKP HCLKN DREFCLK SDM_A0 SDM_A1 SDM_A2 SDM_A3 SDM_A4 SDM_A5 SDM_A6 SDM_A7 HTRDY# RS2# RS0# BREQ0# 10 ms 15 ms 20 ms
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8.2
XOR Chain Definition
The GMCH has 10 XOR chains. The XOR chain outputs are driven out on the output pins as shown in Table 43. During fullwidth testing, XOR chain outputs will be visible on both pins (For example, xor_out0 will be visible on SDM_A0 and SDM_B0). During channel shared mode on the tester, outputs will be visible on their respective channels. (For example, in channel A mode, xor_out0 will be visible on SDM_A0 and the same will be visible on SDM_B0 in channel B mode.)
Table 43. XOR Chain Outputs
XOR Chain xor_out0 xor_out1 xor_out2 xor_out3 xor_out4 xor_out5 xor_out6 xor_out7 xor_out8 xor_out9 xor_out10 xor_out11 DDR Output Pin Channel A SDM_A0 SDM_A1 SDM_A2 SDM_A3 SDM_A4 SDM_A5 SDM_A6 SDM_A7 HTRDY# RS2# RS0# BREQ0# DDR Output Pin Channel B SDM_B0 SDM_B1 SDM_B2 SDM_B3 SDM_B4 SDM_B5 SDM_B6 SDM_B7 BPRI# DEFER# RS1# CPURST#
The following tables show the XOR chain pin mappings and their monitors for the GMCH. Note: Notes for Table 44 through Table 54. 1. Only AGP differential strobes are on different chains but in the same channel group. Other interface strobes are on the same chain since they are not required to be in opposite polarity all the time. All XOR chains can be run in parallel, except chains with AGP strobes (chains 0 and 1, chains 0 and 2, and chains 2 and 4). 2. The channel A and channel B output pins for each chain show the same output. 3. For the multiplexed AGP and DVO signals, only the AGP signal names are listed. Refer to Section 2.5.7 for the DVO-to-AGP signal mapping. 4. For AGP signals, only the AGP 3.0 signal name is listed. For the corresponding AGP 2.0 signal name, refer to Chapter 2.
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Table 44. XOR Chain 0 (60 Inputs) Output Pins: SDM_A0, SDM_B0
Signal Name CI7 CI1 CI2 CI8 CI9 CI0 CISTRF CISTRS CI6 CI3 CI4 CI5 CI10 GAD1 GAD5 GAD0 GAD6 GAD2 GAD4 GAD8 Ball Number AG7 AH7 AD11 AE9 AH9 AK7 AJ6 AJ5 AF8 AF7 AD7 AC10 AG6 AC11 AC9 AE6 AB11 AD5 AA10 AA9 Output Pins SDM_A0 SDM_B0 AP12 AG11 Signal Name GAD3 GC#/BE0 GADSTB0 GAD12 GAD7 GSTOP GAD11 GAD10 GAD9 GAD15 GAD13 GAD14 GTRDY GPAR GC#/BE1 GFRAME DBI_LO GDEVSEL GRBF GWBF Ball Number AE5 Y7 AC6 AA11 AB7 W11 W10 AA5 AA6 V7 W6 W9 AB5 AB2 W5 U6 M5 AB4 R10 R9 Signal Name GST0 GIRDY GC#/BE2 GC#/BE3 GST2 DBI_HI GREQ GSBA2# GSBSTBF GSBA7# GSBA0# GSBA5# GSBA3# GSBA4# GSBA1# GSBA6# DDCA_CLK DDCA_DATA VSYNC RSVD Ball Number N3 V11 AA3 U2 N2 M4 N6 R3 U11 T7 R6 U10 R5 U9 P7 U5 F2 H3 E2 AJ8
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Table 45. XOR Chain 1 (33 Inputs) Output Pins: SDM_A1, SDM_B1
Signal Name HI7 HI4 HI3 HI5 HISTRF HI10 HISTRS HI2 HI0 HI6 HI1 Ball Number AL4 AK5 AG5 AL3 AH5 AJ3 AH4 AK2 AF5 AL2 AG3 Output Pins SDM_A1 SDM_B1 AP16 AG15 Signal Name HI8 HI9 GST1 GAD20 GAD16 GAD17 GAD19 GAD18 GADSTBF1 GAD22 GAD26 Ball Number AJ2 AH2 N5 Y5 AA2 Y4 W2 Y2 V5 W3 T5 Signal Name GAD23 GAD25 GAD27 GAD24 GAD21 GAD28 GAD30 GAD31 GAD29 GGNT EXTTS# Ball Number U3 T4 R2 T2 V2 P2 P4 M2 P5 M7 AP8
Table 46. XOR Chain 2 (44 Inputs) Output Pins: SDM_A2, SDM_B2
Signal Name GADSTBS0 GSBSTBS HD29# HD25# HD26# HD31# HD22# HD17# HD30# HD20# DINVB_1 HD23# HDSTBP1# HDSTBN1# Ball Number AC5 T11 G14 F15 E15 K17 G16 F17 E17 J17 L17 G18 L19 K19 Signal Name HD19# HD27# HD24# HD21# HD28# HD16# HD18# DINV0# HD8# HD11# HD14# HD10# HD15# HD13# HDSTBP0# Output Pins SDM_A2 SDM_B2 AM24 AE21 Ball Number F19 E21 F21 L18 J19 G20 E19 C17 E18 D16 E16 B16 D18 B17 B19 Signal Name HDSTBN0# HD6# HD9# HD12# HD3# HD2# HD0# HD4# HD5# HD7# HD1# PROCHOT# HITM# BSEL0 HLOCK# Ball Number C19 B20 E20 B18 D20 B21 B23 B22 D22 C21 E22 L20 E23 L13 E25
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Table 47. XOR Chain 3 (41 Inputs) Output Pins: SDM_A3, SDM_B3
Signal Name BNR# BSEL1 HIT# DRDY# DBSY# ADS# HREQ4# HA16# HREQ3# HREQ0# HA3# HREQ1# HA7# HA14# Ball Number B28 L12 K21 G24 E27 F27 J21 F25 C29 B29 D26 J23 B32 B33 Output Pins SDM_A3 SDM_B3 AP30 AJ28 HA4# HA10# HA15# HA8# HA13# HA6# HA5# HA11# HREQ2# HA31# HA26# D30 C31 J24 K23 E30 E29 L23 J25 L22 G26 K24 Signal Name HA12# HA9# Ball Number B31 C30 Signal Name HA19# HA18# HA22# HA24# HA23# HADSTB1# HA17# HA25# HA20# HA30# HA21# HA27# HA29# HA28# Ball Number F28 C32 G27 E28 F29 D28 D34 H27 C34 J26 J27 E32 G30 F31
Table 48. XOR Chain 4 (40 Inputs) Output Pins: SDM_A4, SDM_B4
Signal Name HD45# HD46# HD40# HD47# HD39# HD36# HD44# HD42# DINV2# HDSTBP2# HDSTBN2# HD34# HD38# Ball Number H10 G8 G10 E9 G12 F11 J11 E11 L14 G9 F9 J13 K15 Output Pins SDM_A1 SDM_B1 AF31 AC31 Signal Name HD43# HD33# HD41# HD35# HD32# HD37# HD58# HD56# HD62# HD61# HD63# HD59# HD60# Ball Number K13 L16 L15 F13 J15 E13 E10 D10 D8 B9 B8 B10 C9 Signal Name HD57# HDSTBP3# HDSTBN3# HD51# HD49# HD55# HD54# HD53# HD50# HD48# HD52# DINV3# GADSTBF1 HSYNC Ball Number C11 D12 E12 B12 E14 B11 C13 D14 B14 B13 B15 C15 V4 G3
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Table 49. XOR Chain 5 (44 Inputs) Output Pins: SDM_A5, SDM_B5
Signal Name SDQ_A58 SDQ_A59 SDQ_A62 SDQ_A63 SDQS_A7 SDQ_A61 SDQ_A57 SDQ_A56 SDQ_A60 SDQ_A51 SDQ_A50 SDQ_A55 SDQS_A6 SDQ_A54 Ball Number E33 F33 G34 F34 H31 J34 H34 J33 K31 K32 K34 L33 M32 L34 Signal Name SDQ_A53 SDQ_A48 SDQ_A52 SDQ_A49 SCMDCLK_A5# SCMDCLK_A5 SCMDCLK_A2# SCMDCLK_A2 SDQS_A5 SDQ_A42 SDQ_A46 SDQ_A47 SDQ_A43 SDQ_A40 SDQ_A45 Output Pins SDM_A1 SDM_B1 W33 U31 Ball Number P34 T34 T31 T32 P32 P31 N34 N33 V34 V32 U34 U33 V31 AC34 AB32 Signal Name SDQ_A41 SDQ_A44 SDQS_A4 SDQ_A35 SDQ_A38 SDQ_A39 SDQ_A34 SDQ_A33 SDQ_A37 SDQ_A36 SDQ_A32 SCMDCLK_A0 SCMDCLK_A0# SCMDCLK_A3# SCMDCLK_A3 Ball Number AB31 AD31 AF34 AD32 AE34 AD34 AF32 AG34 AG33 AH31 AH32 AK32 AK31 AK34 AK33
Table 50. XOR Chain 6 (40 Inputs) Output Pins: SDM_A6, SDM_B6
Signal Name SDQ_A30 SDQS_A3 SDQ_A27 SDQ_A31 SDQ_A29 SDQ_A26 SDQ_A25 SDQ_A24 SDQ_A28 SDQS_A2 SDQ_A21 SDQ_A17 SDQ_A18 Ball Number AM31 AM30 AM33 AN34 AN29 AP33 AP29 AP28 AM28 AP23 AL22 AM22 AL24 Signal Name SDQ_A19 SDQ_A23 SDQ_A22 SDQ_A16 SDQ_A20 SDQ_A10 SDQ_A15 SDQ_A14 SDQS_A1 SDQ_A11 SDQ_A13 SDQ_A9 SDQ_A12 Ball Number AN27 AP27 AP25 AP22 AP21 AL18 AM18 AP18 AP15 AP19 AN15 AM14 AL14 Signal Name SDQ_A8 SDQ_A6 SDQ_A2 SDQ_A3 SDQS_A0 SDQ_A5 SDQ_A7 SDQ_A4 SCMDCLK_A1 SCMDCLK_A1# SDQ_A1 SCMDCLK_A4# SCMDCLK_A4 SDQ_A0 Output Pins SDM_A6 SDM_B6 M34 M29 Ball Number AP14 AL12 AM12 AN13 AN11 AL10 AP13 AM10 AP17 AN17 AP11 AL16 AM16 AP10
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Table 51. XOR Chain 7 (45 Inputs) Output Pins: SDM_A7, SDM_B7
Signal Name HADSTB1# SDQ_B57 SDQ_B61 SDQ_B58 SDQ_B63 SDQ_B60 SDQS_B7 SDQ_B62 SDQ_B59 SDQ_B56 SDQ_B51 SDQ_B54 SDQ_B55 SDQ_B53 SDQ_B50 Ball Number D28 H29 M25 F32 G32 N25 J30 J29 G33 K30 L30 P25 L32 R26 K28 Output Pins SDM_A7 SDM_B7 H32 J31 Signal Name SDQS_B6 SDQ_B48 SDQ_B49 SDQ_B52 SCMDCLK_B5 SCMDCLK_B5# SCMDCLK_B2# SCMDCLK_B2 SDQ_B43 SDQ_B46 SDQ_B42 SDQ_B47 SDQ_B45 SDQ_B40 SDQ_B44 Ball Number L27 P29 R30 R31 N31 N30 N26 N27 T25 U25 U27 R27 V29 AA30 AA31 Signal Name SDQ_B41 SDQS_B5 SDQ_B37 SDQ_B36 SDQ_B35 SDQ_B32 SDQ_B34 SDQ_B38 SDQ_B33 SDQ_B39 SDQS_B4 SCMDCLK_B0 SCMDCLK_B0# SCMDCLK_B3 SCMDCLK_B3# Ball Number W30 U30 AB29 AE31 Y29 AE30 AC30 AA26 AC27 AA27 AD29 AG29 AG30 AJ30 AH29
Table 52. XOR Chain 8 (40 Inputs) Output Pins: SDM_A8, SDM_B8
Signal Name SDQ_B30 SDQ_B26 SDQ_B29 SDQ_B27 SDQ_B31 SDQ_B25 SDQS_B3 SDQ_B28 SDQ_B24 SDQ_B23 SDQ_B18 SDQ_B19 SDQ_B22 Ball Number AD25 AG27 AJ27 AF27 AF28 AH26 AH27 AJ26 AK25 AE22 AG23 AK23 AJ24 Signal Name SDQ_B21 SDQ_B17 SDQS_B2 SDQ_B16 SDQ_B20 SDQ_B10 SDQ_B14 SDQ_B15 SDQ_B11 SDQ_B13 SDQ_B12 SDQ_B9 SDQS_B1 Ball Number AK21 AE20 AG21 AE19 AL19 AK17 AJ16 AJ18 AL17 AJ14 AK13 AL13 AG13 Signal Name SDQ_B8 SCMDCLK_B4# SCMDCLK_B4 SCMDCLK_B1# SCMDCLK_B1 SDQ_B1 SDQ_B3 SDQ_B7 SDQ_B2 SDQ_B6 SDQ_B5 SDQ_B0 SDQ_B4 SDQS_B0 Output Pins HTRDY# BPRI# D24 B26 Ball Number AE17 AL15 AK15 AG17 AF17 AE15 AE16 AG12 AL11 AK11 AF12 AJ10 AL8 AF15
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Table 53. XOR Chain 9 (62 Inputs) Output Pins: RS2#, DEFER#
Signal Name SCAS_A# SWE_A# SCS_B3# SBA_B1 SBA_A1 SCS_A1# SCS_A2# SCS_A3# SRAS_A# SBA_A0 SCS_A0# SMAA_B2 SRAS_B# SMAA_B10 SBA_B0 SMAA_A10 SMAB_B1 SMAA_A0 SMAA_A1 SMAA_A2 Ball Number Y34 AB34 W25 AA25 AH34 Y31 Y32 W34 AC33 AE33 AA34 AD27 W26 AF29 Y25 AJ33 AE27 AJ34 AL33 AK29 Signal Name SMAA_B0 SMAB_A1 SMAA_A6 SMAA_B6 SMAB_A3 SMAB_A2 SMAA_A3 SMAA_B3 SMAA_B1 SMAB_B3 SMAA_A4 SMAB_B4 SMAB_B2 SMAB_A4 SMAB_A5 SMAA_A9 SMAB_B5 SMAA_A8 SMAA_A5 SMAA_A7 SMAA_B8 Output Pins RS2# DEFER# B27 L21 Ball Number AG31 AL34 AL28 AL25 AP32 AM34 AN31 AE24 AJ31 AL29 AL30 AL27 AD26 AP31 AM26 AP24 AE23 AP26 AL26 AN25 AL23 Signal Name SMAA_B7 SMAA_B9 SMAA_B11 SMAA_B4 SMAA_B5 SCKE_A3 SCKE_A0 SMAA_A11 SMAA_A12 SCKE_A2 SCKE_A1 SCKE_B0 SCKE_B3 SCKE_B2 SMAA_B12 SCKE_B1 SCS_B1# SCS_B0# SCS_B2# SWE_B# SCAS_B# Ball Number AF21 AJ22 AL21 AK27 AG25 AP20 AL20 AN23 AN21 AM20 AN19 AK19 AE18 AG19 AJ20 AF19 T29 U26 V25 W27 W31
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Table 54. XOR Excluded Pins
Signal Name BLUE BLUE# BPRI# BREQ0# CPURST# DEFER# DREFCLK GCLKIN GRCOMP GREEN GREEN# GVREF GVSWING HCLKN HCLKP HDRCOMP HDSWING HDVREF HTRDY# HI_COMP HI_VREF HI_SWING PWROK RED RED# REFSET RS0# RS1# RS2# RSTIN# Ball Number H7 G6 B26 B24 E8 L21 G4 H4 AC2 H6 G5 AD2 AC3 C7 B7 E24 C25 F23 D24 AD4 AE2 AE3 AE14 F4 E4 D2 G22 C27 B27 AK4 Signal Name SDM_A0 SDM_A1 SDM_A2 SDM_A3 SDM_A4 SDM_A5 SDM_A6 SDM_A7 SDM_B0 SDM_B1 SDM_B2 SDM_B3 SDM_B4 SDM_B5 SDM_B6 SDM_B7 SMVREF_A0 SMVREF_B0 SMXRCOMP SMXRCOMPVOH SMXRCOMPVOL SMYRCOMP SMYRCOMPVOH SMYRCOMPVOL Reserved TESTIN# CI_RCOMP CI_VREF CI_VSWING Ball Number AP12 AP16 AM24 AP30 AF31 W33 M34 H32 AG11 AG15 AE21 AJ28 AC31 U31 M29 J31 E34 AP9 AK9 AN9 AL9 AA33 R34 R33 AG9 AG10 AG2 AF4 AF2
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Intel(R) 82865GV GMCH
9
Chapter 1 through Chapter 8 of this datasheet described the 82865G component. The first 8 chapters also apply to the 82865GV, with the differences noted in this chapter. This chapter describes the differences between the 82865G and the 82865GV components. Figure 22 shows an example block diagram of an 865GV chipset-based platform. The information in Chapter 9 through Chapter 11apply to the 82865GV component, unless otherwise noted. Figure 22. Intel(R) 865GV Chipset System Block Diagram
Processor 400/533/800 MHz FSB VGA System Memory Intel (R) 865GV Chipset DDR Channel A 2 DVO ports 2.1 GB/s Intel
(R)
82865GV GMCH
2.1 GB/s up to 3.2 GB/s Channel B 2.1 GB/s up to 3.2 GB/s
DDR
DDR
CSA Interface Gigabit Ethernet
266 MB/s 266 MB/s HI 1.5
DDR
USB 2.0 8 ports, 480 Mb/s
Pow er Management Clock Generation
GPIO Intel (R) 82801EB ICH5 or Intel (R) 82801ER ICH5R LAN Connect/ASF System Management (TCO) SMBus 2.0/I2C Six PCI Masters AC '97 3 CODEC support PCI Bus
2 Serial ATA Ports 150 MB/s
2 ATA 100 Ports
Flash BIOS
LPC Interface
SIO
Sys Blk
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9.1
No AGP Interface
The 82865GV does not have an AGP interface. References to AGP or AGP/PCI_B in this document only apply to the 82865G component. For example, Chapter 2 describes how the 82865G DVO signals are multiplexed with the AGP signals. For the 82865GV, the DVO signals are not multiplexed. In addition, AGP related registers are not in the 82865GV component.
9.2
Intel(R) 82865G / 82865GV Signal Differences
The 82865G and 82865GV signals are the same, except for the following:
* ADD_DETECT signal functionality is slightly different between the two components. * There are no AGP signals on the 82865GV. The 82865GV DVO signals are not multiplexed.
Section 2.5.7, Intel(R) DVO Signals Name to AGP Signal Name Pin Mapping does not apply to the 82865GV. In Section 2.5.5, replace the ADD_DETECT signal description with the following:
Signal Name Type Description PAR: Same as PCI. Not used on AGP transactions but used during PCI transactions as defined by the PCI Local Bus Specification, Revision 2.1. GPAR/ ADD_DETECT I/O AGP ADD_DETECT: This signal acts as a strap and indicates whether the interface is in DVO mode. The 82865GV GMCH has an internal pull-up on this signal that will naturally pull it high. If an Intel(R) DVO is used, the signal should be pulled low and the DVO select bit in the GMCHCFG register will be set to DVO mode. Motherboards that use this interface in a DVO down scenario should have a pull-down resistor on ADD_DETECT.
9.2.1
Functional Straps
In Section 2.11.1, Functional Straps, replace the PSBSEL signal description with the following:
Signal Name Type Description Operating Mode Select Strap: This strap selects the operating mode of the Intel(R) DVO signals GPAR/ ADD_DETECT * 0 (low voltage) = ADD Card (2X DVO) DVO * 1 (high voltage) = Reserved The ADD_DETECT strap is flow-through while RSTIN# is asserted and latched on the deasserting edge of RSTIN#. RSTIN# is used to make sure that the card is not driving the GPAR/ADD_DETECT signal when it is latched.
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9.3
Intel(R) 82865G / 82865GV Register Differences
Chapter 3 describes the registers for the 82865G GMCH. This section describes the changes to Chapter 3 for the 82865GV GMCH. The differences are in the Device 0 and Device 1 register sets. The Device 2 registers are the same for the 82865G and 82865GV.
9.3.1
9.3.1.1
DRAM Controller/Host-Hub Interface Device Registers (Device 0)
Device 0 Registers Not in 82865GV
The following registers are not in the 82865GV and the address locations are Intel Reserved. APBASE
-- Aperture Base Configuration Register (Device 0)
10-13h 32 bits
Address Offset: Size:
AGPM -- AGP Miscellaneous Configuration Register (Device 0) Address Offset Size: 51h 8 bits
ACAPID -- AGP Capability Identifier Register (Device 0) Address Offset Size: A0-A3h 32 bits
AGPSTAT -- AGP Status Register (Device 0) Address Offset Size: A4-A7h 32 bits
AGPCMD -- AGP Command Register (Device 0) Address Offset Size: A8-ABh 32 bits
AGPCTRL -- AGP Control Register (Device 0) Address Offset Size: B0-B3h 32 bits
APSIZE -- Aperture Size Register (Device 0) Address Offset Size: B4h 8 bits
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ATTBASE -- Aperture Translation Table Register (Device 0) Address Offset Size: B8-BBh 32 bits
AMTT -- AGP MTT Control Register (Device 0) Address Offset Size: BC-BFh 8 bits
LPTT -- AGP Low Priority Transaction Timer Register (Device 0) Address Offset Size: BDh 8 bits
9.3.1.2
Device 0 Register Bit Differences
The registers described in this section are in both the 82865G and 82865GV. However, some of the register bits have different functions/operations between the two components. Only the bits that are different are shown in this section. The remaining register bits are the same for both the 82865G and 82865GV and are described in Chapter 3. GC--Graphics Control Register (Device 0)
Address Offset Default Value Access Size:
Bits
52h 0000_0000b RO, R/W. R/W/L 8 bits
Description
3
Integrated Graphics Disable (IGDIS) -- RO. The GMCH's Device 1 is disabled such that all configuration cycles to Device 1 flow through to the hub interface. Also, the Next_Pointer field in the CAPREG register (Device 0, Offset E4h) is RO at 00h. This enables internal graphics capability. 0 = Enable. Internal Graphics is enabled (default)
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GMCHCFG--GMCH Configuration Register (Device 0)
Address Offset Default Value Access Size:
Bits
C6-C7h 0000h R/W, RO 16 bits
Description
AGP Mode (AGP/DVO#)--RO. This bit reflects the ADD_DETECT strap value. This strap bit determines the function of the AGP I/O signal. 0 = 2xDVO 1 = no DVO mode, internal graphics only. 3 When the strap is sampled low, this bit is 0 and Intel(R) DVO mode is selected. When the strap is sampled high, this bit is 1 and DVO mode is not selected, and the internal graphics device is running. Note that when this bit is set to 0 (DVO mode), Device 1 is disabled (configuration cycles fallthrough to the hub interface) and the Next Pointer field in CAPREG will be hardwired to 0s.
ERRSTS--Error Status Register (Device 0)
Address Offset Default Value Access Size:
Bits 4:0 Intel Reserved
C8-C9h 0000h R/WC 16 bits
Description
ERRCMD--Error Command Register (Device 0)
Address Offset Default Value Access Size:
Bits 4:0 Intel Reserved
CA-CBh 0000h RO, R/W 16 bits
Description
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CAPREG--Capability Identification Register (Device 0)
Address Offset Default Value Access Size:
Bits 15:8
E4h-E8h 000001060009h RO 40 bits
Description
Next_Pointer. This field has the value A0h pointing to the next capabilities register, AGP Capability Identifier Register (ACAPID). Since AGP is disabled (IGDIS = 0), this becomes the last pointer in the device, and it is set to 00h signifying the end of the capabilities linked list.
9.3.2
Host-to-AGP Bridge Registers (Device 1)
Device 1 does not exist on the 82865GV component. The Device 1 registers described in Chapter 3 are not in the 82865GV. For the 82865GV, these register address locations are Intel Reserved.
9.4
Synchronous Display Differences
The synchronous display is different between the 82865G and 82865GV. For the 82865GV, replace Section 5.5.3, Synchronous Display with the following: Synchronous Display Microsoft Windows* 98 and Windows* 2000/XP have enabled support for multi-monitor display. Synchronous mode will display the same information on multiple displays. Since the 82865GV GMCH has several display ports available for its single pipe, it can support synchronous display on two displays unless one of the displays is a TV. No synchronous display is available when a TV is in use. The GMCH does not support two synchronous digital displays. The 82865GV GMCH cannot drive multiple displays concurrently (different data or timings). Since the 82865GV GMCH does not support AGP, it is incapable of operating in parallel with an external AGP device. The 82865GV GMCH can, however, work in conjunction with a PCI graphics adapter.
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Intel(R) 82865GV GMCH Ballout
Intel(R) 82865GV GMCH Ballout
10
The chapter provides the ballout for the 82865GV component only. Table 55 provides the 82865GV ballout arranged alphabetically by signal name. The differences between the ballout list in this chapter and the ballout list in Chapter 7 is that the AGP signals have been replaced with their corresponding DVO signal names. Since not all 82865G AGP signals are multiplexed, the remaining non-multiplexed 82865G AGP signals are shown in Table 55 as TESTP[153:140]. The ballout footprint is shown in Figure 23 and Figure 24. These figures represent the ballout arranged by ball number. Table 55 provides the ballout arranged alphabetically by signal name. Note: The following notes apply to the ballout. 1. NC = No Connect 2. RSVD = These reserved balls should not be connected and should be allowed to float. 3. Shaded cells in Figure 23 and Figure 24 do not have a ball.
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Intel(R) 82865GV GMCH Ballout
Figure 23. Intel(R) 82865GV GMCH Ballout Diagram (Top View--Left Side)
35 AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A
NC VSS VSS VSS VSS VSS VCC_DDR VSS VSS VSS VSS VSS RSVD VSS NC RSVD SDQ_A31 SMAB_A2 SDQ_A27 VSS SCMD CLK_A0 VSS SCMD CLK_A0# SMAA_B1 SCMDCLK_ B3 VSS SCMD CLK_B0# VSS SDQ_B32 VSS SDQ_B34 VSS SDQ_B40 VSS SDQ_B41 VSS SDQS_B5 VSS SDQ_B49 VSS SCMD CLK_B5# VSS SDQ_B51 SDQ_B56 VSS SDQ_B50 VSS SDM_B6 VSS SDQ_B48 VSS SCS_B1# VSS SDQ_B45 VSS SDQ_B35 VSS SDQ_B37 VSS SDQS_B4 VSS SCMD CLK_B3# SCMD CLK_B0 SMAA_ B10 VSS
34
33
NC
32
VSS
31
VCC_DDR
30
29
VSS
28
27
VSS
26
25
VSS
24
23
VSS SDQS_A2 SMAA_A11 VSS SMAA_B8 SDQ_B19
22
21
VCC_DDR
20
VSS SCKE_A3 VSS SCKE_A2 SCKE_A0 VSS SMAA_B12 VSS
19
18
SDQ_A26 SMAB_A3 SMAB_A4 VSS SMAA_A3 SDQ_A30
SDM_A3 VSS SDQS_A3
SDQ_A25 SDQ_A24 SDQ_A23 SMAA_A8 SDQ_A22 SMAA_A9 SDQ_A29 VSS VSS SDQ_A28 SDQ_A19 VSS VSS SMAB_A5 SMAA_A7 VSS VSS SDM_A2
SDQ_A16 VSS SDQ_A17 SDQ_A21 VSS SMAA_B9 VSS
SDQ_A20 SMAA_A12 VSS SMAA_B11 SDQ_B21
SDQ_A11 SCKE_A1 VSS SDQ_B20 SCKE_B0
SDQ_A14 VSS SDQ_A15 SDQ_A10 VSS SDQ_B15 VSS
VCCA_DDR SMAB_A1 SMAA_A1 SCMD CLK_A3# SMAA_A0 SBA_A1 SCMD CLK_A3 SMAA_ A10 VSS
SMAA_A4 SMAB_B3 SMAA_A6 SMAB_B4 SMAA_A5 SMAA_B6 SDQ_A18 SMAA_A2 VSS SDM_B3 SMAA_B4 VSS SDQ_B24 VSS SDQ_B22 VSS SMAA_B5 VSS VSS VSS VSS VSS SMAA_B3
SDQ_B29 SDQ_B28 SDQS_B3 SDQ_B25 SDQ_B26 VSS
SDQ_A32 SDQ_A36 VSS SDQ_A34 VSS SMAA_B0 SDM_A4 SDQ_B36
SDQ_A33 SDQ_A37 SDQS_A4 SDQ_A38 SDQ_A39 SDQ_A40 SWE_A# SCS_A0# SCAS_A# SCS_A3# SDQS_A5 VSS SBA_A0 VSS SAS_A# VSS SMYRCO MP VSS SDM_A5 VSS
SDQ_B18 NC SMAB_B5
VSS VSS SDQ_B23
SDQS_B2 SMAA_B7 SDM_B2
VSS VSS SDQ_B17
SCKE_B2 SCKE_B1 SDQ_B16
VSS VSS SCKE_B3
SDQ_B31 SDQ_B27 SMAB_B1
SDQ_A35 SDQ_A44 VSS SDM_B4
SMAA_B2 SMAB_B2 SDQ_B30 SDQ_B33 VSS VCCA_ DDR VSS VCCA_ DDR VCCA_ DDR
SDQ_A45 SDQ_A41 VSS SDQ_B44
SDQ_B39 SDQ_B38 SBA_B1 VSS VSS SBA_B0 VCC VCC VCC VCC VCC VCC VCC VSS VSS VCC VCC VSS VCC VSS VCC
SCS_A2# SCS_A1# VSS SCAS_B#
SWE_B# SRAS_B# SCS_B3# VSS VSS SCS_B2#
SDQ_A42 SDQ_A43 VSS SDM_B5
SDQ_A46 SDQ_A47 SDQ_A48 VSS
SDQ_B42 SCS_B0# SDQ_B46 VSS VSS SDQ_B43 NC SDQ_B54
SDQ_A49 SDQ_A52 VSS SCMD CLK_A5# VSS SDQS_A6 SDQ_B52 SCMDC LK_A5 SCMD CLK_B5 NC VSS
SMYRCOM SMYRCO VCC_DDR PVOH MPVOL SDQ_A53 SCMD CLK_A2# SDM_A6 VSS SCMD CLK_A2 VSS
SDQ_B47 SDQ_B53 VSS SCMD CLK_B2 VSS SDQS_B6 VSS HA21# HA25# VSS HA23# HA19# HA24# HADSTB1# VSS BNR# HA22# ADS# DBSY# VSS RS1# RS2# VSS HA30# VSS HA31# VSS NC HA3# VSS BPRI# VSS
SCMD SDQ_B60 CLK_B2# VSS VSS SDQ_B61 VSS VSS HA11# VSS HA26# HA15# VSS DRDY# HA16# VSS HDVREF HITM# VSS NC HD0# VSS HA5# HA8# HREQ1# HREQ2# VSS VSS VSS RS0# VSS HD1# HD5# VSS HD4# HD24# HD27# VSS HD7# HD2# VTT DEFER# HIT# HREQ4# PROCHOT# HDSTBP1# VSS VSS VSS HD16# VSS HD9# HD3# VSS HD6# VSS HD19# HD18# VSS HDSTBNB_0 HDSTBP0# HDSTBNB_1 HD28# HD21# VSS VSS VSS HD23# VSS HD8# HD15# VSS HD12#
SDQ_A54 SDQ_A55 SDQ_B55 SDQ_A50 VSS
SDQ_A51 SDQ_A60 VSS SDM_A7 SDM_B7 SDQS_A7 VSS HA28#
SDQ_A61 SDQ_A56 SDQ_A57 VSS
SDQS_B7 SDQ_B62 VSS HA29# SDQ_B57
SDQ_A62 SDQ_B59 SDQ_B63 SDQ_A63 SDQ_A59 SDQ_B58
VCC_DDR SMVREF_A SDQ_A58 VSS NC HA17# HA20# NC HA14# NC VSS
HA27# VSS HA18# HA7# VSS HA10# HA12# VCCA_FSB
HA13# HA4# HA9#
HA6# VSS HREQ3#
HLOCK# HDRCOMP VSS HD SWING NC VSS HTRDY# VSS BREQ0#
HADSTB0# HREQ0# VSS
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
228
Intel(R) 82865G/82865GV GMCH Datasheet
Intel(R) 82865GV GMCH Ballout
Figure 24. Intel(R) 82865GV GMCH Ballout Diagram (Top View--Right Side)
17 16
VSS SCMD CLK_A1 SCMD CLK_A1# VSS SDQ_B11 SDQ_B10 SDM_A1 VSS SCMD CLK_A4 SCMD CLK_A4# VSS SDQ_B14 VSS SCMD CLK_B1# SCMD CLK_B1 SDQ_B8 VSS VSS SDQ_B3 SDM_B1 SDQS_B0 SDQ_B1
15
VCC_DDR SDQS_A1 SDQ_A13 VSS SCMD CLK_B4# SCMD CLK_B4
14
13
VSS
12
11
VSS
10
9
VSS
8
7
VCC_DDR
6
5
4
3
NC VCC_DDR
2
1
RSVD
VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR HI4 CISTRF CISTRS HISTRF HI3 HI0 DVOB_D0 HI7 RSTIN# VSS HISTRS VSS CI_VREF VSS
AR AP
SDQ_A8 VSS SDQ_A9 SDQ_A12 VSS SDQ_B13 VSS VSS VSS PWROK
SDQ_A7 SDQ_A3 VSS SDQ_B9 SDQ_B12
SDM_A0 VSS SDQ_A2 SDQ_A6 VSS NC VSS
SDQ_A1 SDQS_A0 VSS SDQ_B2 SDQ_B6
SDQ_A0 VSS SDQ_A4 SDQ_A5 VSS SDQ_B0 VSS
SMVREF_B
EXTTS#
VCC_DDR VCC_DDR VCC_DDR VCC_DDR CI0
NC VCC_DDR NC VCC_DDR VSS
SMXRCOM VCC_DDR PVOH VSS SMXRCOM PVOL SMX RCOMP VSS CI9 RSVD VSS VSS CI6 VCC_DDR SDQ_B4 VSS RSVD
AN AM AL AK
VCC_DDR HI5 VSS HI10 VSS HI1 VSS HI_SWING VSS TESTP141 VSS TESTP140 VSS DVOC_D3 VSS DVOC_D4 VSS ADDID2 VSS TESTP149 VSS VCC_AGP VCC_AGP VCC_AGP DDCA_DATA HSYNC VSS VSS VSSA_DAC VSS VCCA_FSB VCCA_DPLL
VCC_DDR HI6 HI2 HI8 HI9 CI_RCOMP CI_SWING HI_VREF GVREF DVOB CRCOMP TESTP144 DVOC_VSYNC
VSS
AJ AH
CI1 CI7 CI3
VSS CI10 VSS DVOB_ HSYNC
SDQS_B1 NC VSS
SDQ_B7 SDQ_B5 VSS
SDM_B0 VSS VSS CI2 DVOB_ VSYNC DVOB_D5
TESTIN#
VCCA_ AGP
AG AF
VSS VSS CI5 VSS
CI8 VSS DVOB_D2 VSS DVOB_D6 VSS DVOB_ FLDSTL VSS ADDID4 VSS VSS ADDID7 VSS MDDC_ DATA VSS DVOB_D7 VSS DVOB_D4 VSS CI4
VSS
AE AD
VSS DVOB_CLK VSS DVOB_D9 VSS DVOBC_ CLKINT VSS MDVI_DATA VSS ADDID0
DVOB_D1 HI_RCOMP DVOB_ CLK# VSS
VSS
AC AB
MDVI_CLK MI2CDATA DVOB_D8 DVOC_D1 DVOB_ BLANK# DVOC_ CLK# ADDID6 VSS DVOC_HSY NC VSS DVOC_ CLK VSS
DVOB_D10 DVOB_D3 VCC VSS VSS VCC VCC VCC VCC VCC VCC VCC VCCA_AGP VSS
VSS
AA Y W V U
DVOC_BLANK# VCC_AGP DVOC_D0 DVOC_D2 DVOC_D5 DVOC_D7 DVOC_D8 DVOC_D11 TESTP151 DVOC_FLDSTL VCC_AGP VCC_AGP VCC_AGP VSS VCC_DAC DDCA_CLK VSYNC REFSET VCCA_DAC NC VCC_DAC VSS VSS VSS NC VCC_AGP VCC_AGP VSS VSS VSS
MDDC_CLK DVOB_D11 MI2CCLK TESTP145 TESTP146 VCC VCC VCC VCC VSS ADDID5 VSS
DVOC_D9 DVOC_D6 ADDID3 VSS
T R P N M L K J H G F E D C B A
TESTP147 TESTP148 VCC VCC VCC VCC VSS VCC VCC VCC VCC VSS HD45# HD40# VCC VSS HDSTBP2# HDSTBN2# HD47# VSS HD60# HD61# VCC VCC VSS HD46# VSS CPURST# HD62# VSS HD63# VTT VTT VTT HCLKN HCLKP VCC TESTP143 VCC VCC VCC BLUE VSS ADDID1
VSS
DVOBC_ DVOC_D10 INTR# VSS
TESTP142 TESTP150 VSS VCC VCC VCC GREEN BLUE#
TESTP153 TESTP152 VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VSS GREEN# VSS GCLKIN DREFCLK RED RED# VTT VTT VTT
DINV1# HD31# HD20#
HD33# VSS VSS VSS HD22#
HD41# HD38# HD32#
DINV2# VSS VSS VSS HD29#
BSEL0 HD43# HD34#
BSEL1 VSS VSS VSS HD39#
VCC VSS HD44#
HD17# HD30# VSS DINV0# HD13#
VSS HD14# HD11# VSS HD10#
HD25# HD26# VSS DINV3# HD52#
VSS HD49# HD53# VSS HD50#
HD35# HD37# VSS HD54# HD48#
VSS HDSTBN3# HDSTBP3# VSS HD51#
HD36# HD42# VSS HD57# HD55#
VSS HD58# HD56# VSS HD59#
VTT VTT VTT VTT
VSS 17 16
VTT 15 14
VSS 13 12
VSS 11 10
VSS 9 8
VSS 7
VTT 6
VTT 5
VTT 4
NC 3 2 1
Intel(R) 82865G/82865GV GMCH Datasheet
229
Intel(R) 82865GV GMCH Ballout
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230
Intel(R) 82865G/82865GV GMCH Datasheet
Intel(R) 82865GV GMCH Ballout
Table 55. Intel(R) 82865GV Ball List by Signal Name
Signal Name ADDID0 ADDID1 ADDID2 ADDID3 ADDID4 ADDID5 ADDID6 ADDID7 ADS# BLUE BLUE# BNR# BPRI# BREQ0# BSEL0 BSEL1 CI_RCOMP CI_SWING CI_VREF CI0 CI1 CI10 CI2 CI3 CI4 CI5 CI6 CI7 CI8 CI9 CISTRF CISTRS CPURST# DBSY# DDCA_CLK DDCA_DATA DEFER# DINV0# DINV1# DINV2# Ball # R6 P7 R3 R5 U9 U10 U5 T7 F27 H7 G6 B28 B26 B24 L13 L12 AG2 AF2 AF4 AK7 AH7 AG6 AD11 AF7 AD7 AC10 AF8 AG7 AE9 AH9 AJ6 AJ5 E8 E27 F2 H3 L21 C17 L17 L14
Table 55. Intel(R) 82865GV Ball List by Signal Name
Signal Name DINV3# DRDY# DREFCLK DVOB_BLANK# DVOBC_CLKINT DVOBC_INTR# DVOB_CLK DVOB_CLK# DVOBCRCOMP DVOB_D0 DVOB_D1 DVOB_D2 DVOB_D3 DVOB_D4 DVOB_D5 DVOB_D6 DVOB_D7 DVOB_D8 DVOB_D9 DVOB_D10 DVOB_D11 DVOB_FLDSTL DVOB_HSYNC DVOB_VSYNC DVOC_BLANK# DVOC_CLK DVOC_CLK# DVOC_D0 DVOC_D1 DVOC_D2 DVOC_D3 DVOC_D4 DVOC_D5 DVOC_D6 DVOC_D7 DVOC_D8 DVOC_D9 DVOC_D10 DVOC_D11 DVOC_FLDSTL Ball # C15 G24 G4 W5 W6 P4 AC6 AC5 AC2 AE5 AD5 AC9 AA10 AB7 AB11 AA9 Y7 AA5 AA6 AA11 W10 W9 AE6 AC11 Y2 V4 V5 W2 Y5 V2 W3 U3 U2 T4 T2 R2 T5 P5 P2 M2
Table 55. Intel(R) 82865GV Ball List by Signal Name
Signal Name DVOC_HSYNC DVOC_VSYNC EXTTS# GCLKIN GREEN GREEN# GVREF HA3# HA4# HA5# HA6# HA7# HA8# HA9# HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31# HADSTB0# HADSTB1# HCLKN HCLKP Ball # Y4 AA2 AP8 H4 H6 G5 AD2 D26 D30 L23 E29 B32 K23 C30 C31 J25 B31 E30 B33 J24 F25 D34 C32 F28 C34 J27 G27 F29 E28 H27 K24 E32 F31 G30 J26 G26 B30 D28 C7 B7
Intel(R) 82865G/82865GV GMCH Datasheet
231
Intel(R) 82865GV GMCH Ballout
Table 55. Intel(R) 82865GV Ball List by Signal Name
Signal Name HD0# HD1# HD2# HD3# HD4# HD5# HD6# HD7# HD8# HD9# HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# HD19# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# Ball # B23 E22 B21 D20 B22 D22 B20 C21 E18 E20 B16 D16 B18 B17 E16 D18 G20 F17 E19 F19 J17 L18 G16 G18 F21 F15 E15 E21 J19 G14 E17 K17 J15 L16 J13 F13 F11 E13 K15 G12
Table 55. Intel(R) 82865GV Ball List by Signal Name
Signal Name HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49# HD50# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# HD59# HD60# HD61# HD62# HD63# HDRCOMP HDSTBN0# HDSTBN1# HDSTBN2# HDSTBN3# HDSTBP0# HDSTBP1# HDSTBP2# HDSTBP3# HDSWING HDVREF HI_RCOMP HI_SWING HI_VREF HI0 HI1 Ball # G10 L15 E11 K13 J11 H10 G8 E9 B13 E14 B14 B12 B15 D14 C13 B11 D10 C11 E10 B10 C9 B9 D8 B8 E24 C19 K19 F9 E12 B19 L19 G9 D12 C25 F23 AD4 AE3 AE2 AF5 AG3
Table 55. Intel(R) 82865GV Ball List by Signal Name
Signal Name HI2 HI3 HI4 HI5 HI6 HI7 HI8 HI9 HI10 HISTRF HISTRS HIT# HITM# HLOCK# HREQ0# HREQ1# HREQ2# HREQ3# HREQ4# HSYNC HTRDY# MDDC_CLK MDDC_DATA MDVI_CLK MDVI_DATA MI2CCLK MI2CDATA NC NC NC NC NC NC NC NC NC NC NC NC NC Ball # AK2 AG5 AK5 AL3 AL2 AL4 AJ2 AH2 AJ3 AH5 AH4 K21 E23 E25 B29 J23 L22 C29 J21 G3 D24 W11 V7 AB5 U6 V11 AB4 A3 A33 A35 AF13 AF23 AJ12 AN1 AP2 AR3 AR33 AR35 B2 B25
232
Intel(R) 82865G/82865GV GMCH Datasheet
Intel(R) 82865GV GMCH Ballout
Table 55. Intel(R) 82865GV Ball List by Signal Name
Signal Name NC NC NC NC NC NC NC PROCHOT# PWROK RED RED# REFSET RS0# RS1# RS2# RSTIN# RSVD RSVD RSVD RSVD RSVD TESTIN# SBA_A0 SBA_A1 SBA_B0 SBA_B1 SCAS_A# SCAS_B# SCKE_A0 SCKE_A1 SCKE_A2 SCKE_A3 SCKE_B0 SCKE_B1 SCKE_B2 SCKE_B3 SCMDCLK_A0 SCMDCLK_A0# SCMDCLK_A1 SCMDCLK_A1# Ball # B34 C1 C23 C35 E26 M31 R25 L20 AE14 F4 E4 D2 G22 C27 B27 AK4 AJ8 AR1 AP34 AG9 AN35 AG10 AE33 AH34 Y25 AA25 Y34 W31 AL20 AN19 AM20 AP20 AK19 AF19 AG19 AE18 AK32 AK31 AP17 AN17
Table 55. Intel(R) 82865GV Ball List by Signal Name
Signal Name SCMDCLK_A2 SCMDCLK_A2# SCMDCLK_A3 SCMDCLK_A3# SCMDCLK_A4 SCMDCLK_A4# SCMDCLK_A5 SCMDCLK_A5# SCMDCLK_B0 SCMDCLK_B0# SCMDCLK_B1 SCMDCLK_B1# SCMDCLK_B2 SCMDCLK_B2# SCMDCLK_B3 SCMDCLK_B3# SCMDCLK_B4 SCMDCLK_B4# SCMDCLK_B5 SCMDCLK_B5# SCS_A0# SCS_A1# SCS_A2# SCS_A3# SCS_B0# SCS_B1# SCS_B2# SCS_B3# SDM_A0 SDM_A1 SDM_A2 SDM_A3 SDM_A4 SDM_A5 SDM_A6 SDM_A7 SDM_B0 SDM_B1 SDM_B2 SDM_B3 Ball # N33 N34 AK33 AK34 AM16 AL16 P31 P32 AG29 AG30 AF17
AG17
Table 55. Intel(R) 82865GV Ball List by Signal Name
Signal Name SDM_B4 SDM_B5 SDM_B6 SDM_B7 SDQ_A_17 SDQ_A0 SDQ_A1 SDQ_A2 SDQ_A3 SDQ_A4 SDQ_A5 SDQ_A6 SDQ_A7 SDQ_A8 SDQ_A9 SDQ_A10 SDQ_A11 SDQ_A12 SDQ_A13 SDQ_A14 SDQ_A15 SDQ_A16 SDQ_A18 SDQ_A19 SDQ_A20 SDQ_A21 SDQ_A22 SDQ_A23 SDQ_A24 SDQ_A25 SDQ_A26 SDQ_A27 SDQ_A28 SDQ_A29 SDQ_A30 SDQ_A31 SDQ_A32 SDQ_A33 SDQ_A34 SDQ_A35 Ball # AC31 U31 M29 J31 AM22 AP10 AP11 AM12 AN13 AM10 AL10 AL12 AP13 AP14 AM14 AL18 AP19 AL14 AN15 AP18 AM18 AP22 AL24 AN27 AP21 AL22 AP25 AP27 AP28 AP29 AP33 AM33 AM28 AN29 AM31 AN34 AH32 AG34 AF32 AD32
N27 N26 AJ30 AH29 AK15 AL15 N31 N30 AA34 Y31 Y32 W34 U26 T29 V25 W25 AP12 AP16 AM24 AP30 AF31 W33 M34 H32 AG11 AG15 AE21 AJ28
Intel(R) 82865G/82865GV GMCH Datasheet
233
Intel(R) 82865GV GMCH Ballout
Table 55. Intel(R) 82865GV Ball List by Signal Name
Signal Name SDQ_A36 SDQ_A37 SDQ_A38 SDQ_A39 SDQ_A40 SDQ_A41 SDQ_A42 SDQ_A43 SDQ_A44 SDQ_A45 SDQ_A46 SDQ_A47 SDQ_A48 SDQ_A49 SDQ_A50 SDQ_A51 SDQ_A52 SDQ_A53 SDQ_A54 SDQ_A55 SDQ_A56 SDQ_A57 SDQ_A58 SDQ_A59 SDQ_A60 SDQ_A61 SDQ_A62 SDQ_A63 SDQ_B0 SDQ_B1 SDQ_B2 SDQ_B3 SDQ_B4 SDQ_B5 SDQ_B6 SDQ_B7 SDQ_B8 SDQ_B9 SDQ_B10 SDQ_B11 Ball # AH31 AG33 AE34 AD34 AC34 AB31 V32 V31 AD31 AB32 U34 U33 T34 T32 K34 K32 T31 P34 L34 L33 J33 H34 E33 F33 K31 J34 G34 F34 AJ10 AE15 AL11 AE16 AL8 AF12 AK11 AG12 AE17 AL13 AK17 AL17
Table 55. Intel(R) 82865GV Ball List by Signal Name
Signal Name SDQ_B12 SDQ_B13 SDQ_B14 SDQ_B15 SDQ_B16 SDQ_B17 SDQ_B18 SDQ_B19 SDQ_B20 SDQ_B21 SDQ_B22 SDQ_B23 SDQ_B24 SDQ_B25 SDQ_B26 SDQ_B27 SDQ_B28 SDQ_B29 SDQ_B30 SDQ_B31 SDQ_B32 SDQ_B33 SDQ_B34 SDQ_B35 SDQ_B36 SDQ_B37 SDQ_B38 SDQ_B39 SDQ_B40 SDQ_B41 SDQ_B42 SDQ_B43 SDQ_B44 SDQ_B45 SDQ_B46 SDQ_B47 SDQ_B48 SDQ_B49 SDQ_B50 SDQ_B51 Ball # AK13 AJ14 AJ16 AJ18 AE19 AE20 AG23 AK23 AL19 AK21 AJ24 AE22 AK25 AH26 AG27 AF27 AJ26 AJ27
AD25
Table 55. Intel(R) 82865GV Ball List by Signal Name
Signal Name SDQ_B52 SDQ_B53 SDQ_B54 SDQ_B55 SDQ_B56 SDQ_B57 SDQ_B58 SDQ_B59 SDQ_B60 SDQ_B61 SDQ_B62 SDQ_B63 SDQS_A0 SDQS_A1 SDQS_A2 SDQS_A3 SDQS_A4 SDQS_A5 SDQS_A6 SDQS_A7 SDQS_B0 SDQS_B1 SDQS_B2 SDQS_B3 SDQS_B4 SDQS_B5 SDQS_B6 SDQS_B7 SMAA_A0 SMAA_A1 SMAA_A2 SMAA_A3 SMAA_A4 SMAA_A5 SMAA_A6 SMAA_A7 SMAA_A8 SMAA_A9 SMAA_A10 SMAA_A11 Ball # R31 R26 P25 L32 K30 H29 F32 G33 N25 M25 J29 G32 AN11 AP15 AP23 AM30 AF34 V34 M32 H31 AF15 AG13 AG21 AH27 AD29 U30 L27 J30 AJ34 AL33 AK29
AN31
AF28 AE30 AC27 AC30 Y29 AE31 AB29 AA26 AA27 AA30 W30 U27 T25 AA31 V29 U25 R27 P29 R30 K28 L30
AL30 AL26 AL28 AN25 AP26 AP24 AJ33 AN23
234
Intel(R) 82865G/82865GV GMCH Datasheet
Intel(R) 82865GV GMCH Ballout
Table 55. Intel(R) 82865GV Ball List by Signal Name
Signal Name SMAA_A12 SMAA_B0 SMAA_B1 SMAA_B2 SMAA_B3 SMAA_B4 SMAA_B5 SMAA_B6 SMAA_B7 SMAA_B8 SMAA_B9 SMAA_B10 SMAA_B11 SMAA_B12 SMAB_A1 SMAB_A2 SMAB_A3 SMAB_A4 SMAB_A5 SMAB_B1 SMAB_B2 SMAB_B3 SMAB_B4 SMAB_B5 SMVREF_A SMVREF_B SMXRCOMP SMXRCOMPVOH SMXRCOMPVOL SMYRCOMP SMYRCOMPVOH SMYRCOMPVOL SRAS_A# SRAS_B# SWE_A# SWE_B# TESTP140 TESTP141 TESTP142 TESTP143 Ball # AN21
AG31
Table 55. Intel(R) 82865GV Ball List by Signal Name
Signal Name TESTP144 TESTP145 TESTP146 TESTP147 TESTP148 TESTP149 TESTP150 TESTP151 TESTP152 TESTP153 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Ball # AB2 U11 T11 R10 R9 N3 N5 N2 M4 M5 J7 J6 J8 J9 K6 K7 K8 K9 L10 L11 L6 L7 L9 M10 M11 M8 M9 N10 N11 N9 P10 P11 R11 T16 T17 T18 T19 T20 U16 U17
Table 55. Intel(R) 82865GV Ball List by Signal Name
Signal Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_DAC VCC_DAC VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR Ball # U20 V16 V18 V20 W16 W19 W20 Y16 Y17 Y18 Y19 Y20 J1 J2 J3 J4 J5 K2 K3 K4 K5 L1 L2 L3 L4 L5 Y1 G1 G2 AA35 AL6 AL7 AM1 AM2 AM3 AM5 AM6 AM7 AM8 AN2
AJ31
AD27
AE24 AK27 AG25 AL25 AF21 AL23 AJ22 AF29 AL21 AJ20 AL34 AM34 AP32 AP31 AM26 AE27 AD26 AL29 AL27 AE23 E34 AP9 AK9 AN9 AL9 AA33 R34 R33 AC33 W26 AB34 W27 AA3 AC3 N6 M7
Intel(R) 82865G/82865GV GMCH Datasheet
235
Intel(R) 82865GV GMCH Ballout
Table 55. Intel(R) 82865GV Ball List by Signal Name
Signal Name VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCCA_AGP VCCA_AGP VCCA_DAC VCCA_DDR VCCA_DDR VCCA_DDR VCCA_DDR VCCA_DPLL VCCA_FSB VCCA_FSB VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # AN4 AN5 AN6 AN7 AN8 AP3 AP4 AP5 AP6 AP7
AR15 AR21
Table 55. Intel(R) 82865GV Ball List by Signal Name
Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # AG24 AG26 AG28 AG32 AG35 AG4 AG8 AH10 AH12 AH14 AH16 AH18 AN30 AN32 AR11 AR13 AR16
AR20 AR23 AR25 AR27 AR29 AR32
Table 55. Intel(R) 82865GV Ball List by Signal Name
Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # D17 D19 K29 K33 L24 L25 L26 L31 L35 M26 M27 M28 M3 M30 M33 M6 N1 N32 N35 N4 P26 P27 P28 P3 P30 P33 P6 P8 P9 R1 R32 R4 T1 T10 A11 A13 A16 A20 A23 A25
AR31 AR4 AR5 AR7 E35 R35 AG1 Y11 C2
AC26
AL35 AB25
AC25
AR9 C10 C12 C14 C16 C18 C20 C22 C24 C26 C28 C4 C8 D1 D11 D13 D15
B3 A31 B4 AF24 AF25 AF3 AF30 AF33 AF6 AF9
AG14 AG16
AG18 AG20 AG22
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Intel(R) 82865GV GMCH Ballout
Table 55. Intel(R) 82865GV Ball List by Signal Name
Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # A27 A29 A32 A7 A9 AA1 AA32 AA4 AB10 AB26 AB27 AB28 AB3 AB30 AB33 AB6 AB8 AB9
AH20 AH22 AH24
Table 55. Intel(R) 82865GV Ball List by Signal Name
Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # AK3 AK8 D21 D23 D25 D27 D29 D31 D33 D35 D9 E1 E3 F1 F10 F12 F14 F16 F18 F20 F22 F24 F26 F3 F5 F8 G28 G31 G35 H12 H14 H16 T26 T27 T28 T3 T30 T33 T35 T6
Table 55. Intel(R) 82865GV Ball List by Signal Name
Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # T8 T9 U18 U19 U32 U4 V10 V17 V19 V26 V27 V28 V3 V30 V33 V6 V8 V9 W17 W18 W32 W4 Y10 Y26 AC1 AC32 AC35 AC4 AD10 AD28 AD3 AD30 AD33 AD6 AD8 AD9 AE1 AE10 AE11 AE12
AH3 AH30 AH33 AH6 AJ1 AJ32 AJ35 AJ4 AJ9 AK10 AK12 AK14 AK16 AK18 AK20 AK22 AK24 AK26 AK28
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Intel(R) 82865GV GMCH Ballout
Table 55. Intel(R) 82865GV Ball List by Signal Name
Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # AE13 AE25 AE26 AE32 AE35 AE4 AF11 AF14 AF16 AF18 AF20 AF22 AL1 AL32
AM11 AM13
Table 55. Intel(R) 82865GV Ball List by Signal Name
Signal Name VSS VSS VSS VSS Ball # H24 H26 H30 H33
Table 55. Intel(R) 82865GV Ball List by Signal Name
Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball # H5 H8 H9 J10 J12 J14 J16 J18 J20 J22 J28 J32 J35 K11 K12 K14 K16 K18 K20 K22 K25 K27 Y27 Y28
AM15 AM17 AM19
AM21 AM23
AM25 AM27 AM29 AM35 AM9
AN10 AN12 AN14 AN16 AN18
AN20
AN22 AN24
AN26 AN28 H18 H2 H20 H22
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Intel(R) 82865GV GMCH Ballout
Table 55. Intel(R) 82865GV Ball List by Signal Name
Signal Name VSS VSS VSS VSS VSS VSS VSS VSSA_DAC VSYNC VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT Ball # Y3 Y30 Y33 Y35 Y6 Y8 Y9 D3 E2 A15 A21 A4 A5 A6 B5 B6 C5 C6 D5 D6 D7 E6 E7 F7
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Intel(R) 82865GV GMCH Ballout
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Intel(R) 82865GV GMCH Testability
Intel(R) 82865GV GMCH Testability
11
The chapter provides the testability for the 82865GV component only. In the GMCH, testability for Automated Test Equipment (ATE) board level testing has been implemented as an XOR chain. An XOR-tree is a chain of XOR gates, each with one input pin connected to it.
11.1
XOR Test Mode Initialization
XOR test mode can be entered by driving ADDID6, ADDID7, TESTIN#, PWROK low, and RSTIN# low, then driving PWROK high, then RSTIN# high. XOR test mode via TESTIN# does not require a clock. But toggling of HCLKP and HCLKN as shown in Figure 25 is required for deterministic XOR operation when in AGP 2.0 mode. If the component is in AGP 3.0 mode, ADDID6, ADDID7, and DVOB_BLANK#must be driven high.
Figure 25. XOR Toggling of HCLKP and HCLKN
1 ms PWROK TESTIN# ADDID6
MDVI_DATA RSTIN#
GCLKIN HCLKP HCLKN DREFCLK
Pin testing will not start until RSTIN# is deasserted. Figure 26 shows chains that are tested sequentially. Note that for the GMCH, sequential testing is not required. All chains can be tested in parallel for test time reduction.
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Figure 26. XOR Testing Chains Tested Sequentially
5 ms PWROK TESTIN# RSTIN# ADDID6 MDVI_DATA GCLKIN HCLKP HCLKN DREFCLK SDM_A0 SDM_A1 SDM_A2 SDM_A3 SDM_A4 SDM_A5 SDM_A6 SDM_A7 HTRDY# RS2# RS0# BREQ0# 10 ms 15 ms 20 ms
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11.2
XOR Chain Definition
The GMCH has 10 XOR chains. The XOR chain outputs are driven out on the output pins as shown in Table 56. During fullwidth testing, XOR chain outputs will be visible on both pins (For example, xor_out0 will be visible on SDM_A0 and SDM_B0). During channel shared mode on the tester, outputs will be visible on their respective channels. (For example, in channel A mode, xor_out0 will be visible on SDM_A0 and the same will be visible on SDM_B0 in channel B mode.)
Table 56. XOR Chain Outputs
XOR Chain xor_out0 xor_out1 xor_out2 xor_out3 xor_out4 xor_out5 xor_out6 xor_out7 xor_out8 xor_out9 xor_out10 xor_out11 DDR Output Pin Channel A SDM_A0 SDM_A1 SDM_A2 SDM_A3 SDM_A4 SDM_A5 SDM_A6 SDM_A7 HTRDY# RS2# RS0# BREQ0# DDR Output Pin Channel B SDM_B0 SDM_B1 SDM_B2 SDM_B3 SDM_B4 SDM_B5 SDM_B6 SDM_B7 BPRI# DEFER# RS1# CPURST#
The following tables show the XOR chain pin mappings and their monitors for the GMCH. Note: Notes for Table 57 through Table 67. 1. All XOR chains can be run in parallel, except chains 0 and 1, chains 0 and 2, and chains 2 and 4). 2. The channel A and channel B output pins for each chain show the same output.
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Table 57. XOR Chain 0 (60 Inputs) Output Pins: SDM_A0, SDM_B0
Signal Name CI7 CI1 CI2 CI8 CI9 CI0 CISTRF CISTRS CI6 CI3 CI4 CI5 CI10 DVOB_VSYNC DVOB_D2 DVOB_HSYNC DVOB_D5 DVOB_D1 DVOB_D3 DVOB_D6 Ball Number AG7 AH7 AD11 AE9 AH9 AK7 AJ6 AJ5 AF8 AF7 AD7 AC10 AG6 AC11 AC9 AE6 AB11 AD5 AA10 AA9 Signal Name DVOB_D0 DVOB_D7 DVOB_CLK DVOB_D10 DVOB_D4 MDDC_CLK DVOB_D11 DVOB_D8 DVOB_D9 MDDC_DATA DVOBC_CLKINT DVOB_FLDSTL MDVI_CLK TESTP144 DVOB_BLANK# MDVI_DATA TESTP153 MI2CDATA TESTP147 TESTP148 Ball Number AE5 Y7 AC6 AA11 AB7 W11 W10 AA5 AA6 V7 W6 W9 AB5 AB2 W5 U6 M5 AB4 R10 R9 Signal Name TESTP149 MI2CCLK TESTP140 DVODC5 TESTP151 TESTP152 TESTP142 ADDID2 TESTP145 ADDID7 ADDID0 ADDID5 ADDID3 ADDID4 ADDID1 ADDID6 DDCA_CLK DDCA_DATA VSYNC RSVD Ball Number N3 V11 AA3 U2 N2 M4 N6 R3 U11 T7 R6 U10 R5 U9 P7 U5 F2 H3 E2 AJ8
Output Pins SDM_A0 SDM_B0 AP12 AG11
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Table 58. XOR Chain 1 (33 Inputs) Output Pins: SDM_A1, SDM_B1
Signal Name HI7 HI4 HI3 HI5 HISTRF HI10 HISTRS HI2 HI0 HI6 HI1 Ball Number AL4 AK5 AG5 AL3 AH5 AJ3 AH4 AK2 AF5 AL2 AG3 Output Pins SDM_A1 SDM_B1 AP16 AG15 Signal Name HI8 HI9 TESTP150 DVOC_D1 DVOC_VSYNC DVOC_HSYNC DVOC_D0 DVOC_BLANK# DVOC_CLK# DVOC_D3 DVOC_D9 Ball Number AJ2 AH2 N5 Y5 AA2 Y4 W2 Y2 V5 W3 T5 Signal Name DVOC_D4 DVOC_D6 DVOC_D8 DVOC_D7 DVOC_D2 DVOC_D11 DVOB_CINTR# DVOC_FLDSTL DVOC_D10 TESTP143 EXTTS# Ball Number U3 T4 R2 T2 V2 P2 P4 M2 P5 M7 AP8
Table 59. XOR Chain 2 (44 Inputs) Output Pins: SDM_A2, SDM_B2
Signal Name DVOB_CLK# TESTP146 HD29# HD25# HD26# HD31# HD22# HD17# HD30# HD20# DINVB_1 HD23# HDSTBP1# HDSTBN1# Ball Number AC5 T11 G14 F15 E15 K17 G16 F17 E17 J17 L17 G18 L19 K19 Signal Name HD19# HD27# HD24# HD21# HD28# HD16# HD18# DINV0# HD8# HD11# HD14# HD10# HD15# HD13# HDSTBP0# Output Pins SDM_A2 SDM_B2 AM24 AE21 Ball Number F19 E21 F21 L18 J19 G20 E19 C17 E18 D16 E16 B16 D18 B17 B19 Signal Name HDSTBN0# HD6# HD9# HD12# HD3# HD2# HD0# HD4# HD5# HD7# HD1# PROCHOT# HITM# BSEL0 HLOCK# Ball Number C19 B20 E20 B18 D20 B21 B23 B22 D22 C21 E22 L20 E23 L13 E25
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Table 60. XOR Chain 3 (41 Inputs) Output Pins: SDM_A3, SDM_B3
Signal Name BNR# BSEL1 HIT# DRDY# DBSY# ADS# HREQ4# HA16# HREQ3# HREQ0# HA3# HREQ1# HA7# HA14# Ball Number B28 L12 K21 G24 E27 F27 J21 F25 C29 B29 D26 J23 B32 B33 Output Pins SDM_A3 SDM_B3 AP30 AJ28 HA4# HA10# HA15# HA8# HA13# HA6# HA5# HA11# HREQ2# HA31# HA26# D30 C31 J24 K23 E30 E29 L23 J25 L22 G26 K24 Signal Name HA12# HA9# Ball Number B31 C30 Signal Name HA19# HA18# HA22# HA24# HA23# HADSTB1# HA17# HA25# HA20# HA30# HA21# HA27# HA29# HA28# Ball Number F28 C32 G27 E28 F29 D28 D34 H27 C34 J26 J27 E32 G30 F31
Table 61. XOR Chain 4 (40 Inputs) Output Pins: SDM_A4, SDM_B4
Signal Name HD45# HD46# HD40# HD47# HD39# HD36# HD44# HD42# DINV2# HDSTBP2# HDSTBN2# HD34# HD38# Ball Number H10 G8 G10 E9 G12 F11 J11 E11 L14 G9 F9 J13 K15 Output Pins SDM_A1 SDM_B1 AF31 AC31 Signal Name HD43# HD33# HD41# HD35# HD32# HD37# HD58# HD56# HD62# HD61# HD63# HD59# HD60# Ball Number K13 L16 L15 F13 J15 E13 E10 D10 D8 B9 B8 B10 C9 Signal Name HD57# HDSTBP3# HDSTBN3# HD51# HD49# HD55# HD54# HD53# HD50# HD48# HD52# DINV3# DVOC_CLK HSYNC Ball Number C11 D12 E12 B12 E14 B11 C13 D14 B14 B13 B15 C15 V4 G3
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Table 62. XOR Chain 5 (44 Inputs) Output Pins: SDM_A5, SDM_B5
Signal Name SDQ_A58 SDQ_A59 SDQ_A62 SDQ_A63 SDQS_A7 SDQ_A61 SDQ_A57 SDQ_A56 SDQ_A60 SDQ_A51 SDQ_A50 SDQ_A55 SDQS_A6 SDQ_A54 Ball Number E33 F33 G34 F34 H31 J34 H34 J33 K31 K32 K34 L33 M32 L34 Signal Name SDQ_A53 SDQ_A48 SDQ_A52 SDQ_A49 SCMDCLK_A5# SCMDCLK_A5 SCMDCLK_A2# SCMDCLK_A2 SDQS_A5 SDQ_A42 SDQ_A46 SDQ_A47 SDQ_A43 SDQ_A40 SDQ_A45 Output Pins SDM_A1 SDM_B1 W33 U31 Ball Number P34 T34 T31 T32 P32 P31 N34 N33 V34 V32 U34 U33 V31 AC34 AB32 Signal Name SDQ_A41 SDQ_A44 SDQS_A4 SDQ_A35 SDQ_A38 SDQ_A39 SDQ_A34 SDQ_A33 SDQ_A37 SDQ_A36 SDQ_A32 SCMDCLK_A0 SCMDCLK_A0# SCMDCLK_A3# SCMDCLK_A3 Ball Number AB31 AD31 AF34 AD32 AE34 AD34 AF32 AG34 AG33 AH31 AH32 AK32 AK31 AK34 AK33
Table 63. XOR Chain 6 (40 Inputs) Output Pins: SDM_A6, SDM_B6
Signal Name SDQ_A30 SDQS_A3 SDQ_A27 SDQ_A31 SDQ_A29 SDQ_A26 SDQ_A25 SDQ_A24 SDQ_A28 SDQS_A2 SDQ_A21 SDQ_A17 SDQ_A18 Ball Number AM31 AM30 AM33 AN34 AN29 AP33 AP29 AP28 AM28 AP23 AL22 AM22 AL24 Signal Name SDQ_A19 SDQ_A23 SDQ_A22 SDQ_A16 SDQ_A20 SDQ_A10 SDQ_A15 SDQ_A14 SDQS_A1 SDQ_A11 SDQ_A13 SDQ_A9 SDQ_A12 Ball Number AN27 AP27 AP25 AP22 AP21 AL18 AM18 AP18 AP15 AP19 AN15 AM14 AL14 Signal Name SDQ_A8 SDQ_A6 SDQ_A2 SDQ_A3 SDQS_A0 SDQ_A5 SDQ_A7 SDQ_A4 SCMDCLK_A1 SCMDCLK_A1# SDQ_A1 SCMDCLK_A4# SCMDCLK_A4 SDQ_A0 Output Pins SDM_A6 SDM_B6 M34 M29 Ball Number AP14 AL12 AM12 AN13 AN11 AL10 AP13 AM10 AP17 AN17 AP11 AL16 AM16 AP10
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Table 64. XOR Chain 7 (45 Inputs) Output Pins: SDM_A7, SDM_B7
Signal Name HADSTB1# SDQ_B57 SDQ_B61 SDQ_B58 SDQ_B63 SDQ_B60 SDQS_B7 SDQ_B62 SDQ_B59 SDQ_B56 SDQ_B51 SDQ_B54 SDQ_B55 SDQ_B53 SDQ_B50 Ball Number D28 H29 M25 F32 G32 N25 J30 J29 G33 K30 L30 P25 L32 R26 K28 Output Pins SDM_A7 SDM_B7 H32 J31 Signal Name SDQS_B6 SDQ_B48 SDQ_B49 SDQ_B52 SCMDCLK_B5 SCMDCLK_B5# SCMDCLK_B2# SCMDCLK_B2 SDQ_B43 SDQ_B46 SDQ_B42 SDQ_B47 SDQ_B45 SDQ_B40 SDQ_B44 Ball Number L27 P29 R30 R31 N31 N30 N26 N27 T25 U25 U27 R27 V29 AA30 AA31 Signal Name SDQ_B41 SDQS_B5 SDQ_B37 SDQ_B36 SDQ_B35 SDQ_B32 SDQ_B34 SDQ_B38 SDQ_B33 SDQ_B39 SDQS_B4 SCMDCLK_B0 SCMDCLK_B0# SCMDCLK_B3 SCMDCLK_B3# Ball Number W30 U30 AB29 AE31 Y29 AE30 AC30 AA26 AC27 AA27 AD29 AG29 AG30 AJ30 AH29
Table 65. XOR Chain 8 (40 Inputs) Output Pins: HTRDY#, BPRI#
Signal Name SDQ_B30 SDQ_B26 SDQ_B29 SDQ_B27 SDQ_B31 SDQ_B25 SDQS_B3 SDQ_B28 SDQ_B24 SDQ_B23 SDQ_B18 SDQ_B19 SDQ_B22 Ball Number AD25 AG27 AJ27 AF27 AF28 AH26 AH27 AJ26 AK25 AE22 AG23 AK23 AJ24 Signal Name SDQ_B21 SDQ_B17 SDQS_B2 SDQ_B16 SDQ_B20 SDQ_B10 SDQ_B14 SDQ_B15 SDQ_B11 SDQ_B13 SDQ_B12 SDQ_B9 SDQS_B1 Ball Number AK21 AE20 AG21 AE19 AL19 AK17 AJ16 AJ18 AL17 AJ14 AK13 AL13 AG13 Signal Name SDQ_B8 SCMDCLK_B4# SCMDCLK_B4 SCMDCLK_B1# SCMDCLK_B1 SDQ_B1 SDQ_B3 SDQ_B7 SDQ_B2 SDQ_B6 SDQ_B5 SDQ_B0 SDQ_B4 SDQS_B0 Output Pins HTRDY# BPRI# D24 B26 Ball Number AE17 AL15 AK15 AG17 AF17 AE15 AE16 AG12 AL11 AK11 AF12 AJ10 AL8 AF15
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Table 66. XOR Chain 9 (62 Inputs) Output Pins: RS2#, DEFER#
Signal Name SCAS_A# SWE_A# SCS_B3# SBA_B1 SBA_A1 SCS_A1# SCS_A2# SCS_A3# SRAS_A# SBA_A0 SCS_A0# SMAA_B2 SRAS_B# SMAA_B10 SBA_B0 SMAA_A10 SMAB_B1 SMAA_A0 SMAA_A1 SMAA_A2 Ball Number Y34 AB34 W25 AA25 AH34 Y31 Y32 W34 AC33 AE33 AA34 AD27 W26 AF29 Y25 AJ33 AE27 AJ34 AL33 AK29 Signal Name SMAA_B0 SMAB_A1 SMAA_A6 SMAA_B6 SMAB_A3 SMAB_A2 SMAA_A3 SMAA_B3 SMAA_B1 SMAB_B3 SMAA_A4 SMAB_B4 SMAB_B2 SMAB_A4 SMAB_A5 SMAA_A9 SMAB_B5 SMAA_A8 SMAA_A5 SMAA_A7 SMAA_B8 Output Pins RS2# DEFER# B27 L21 Ball Number AG31 AL34 AL28 AL25 AP32 AM34 AN31 AE24 AJ31 AL29 AL30 AL27 AD26 AP31 AM26 AP24 AE23 AP26 AL26 AN25 AL23 Signal Name SMAA_B7 SMAA_B9 SMAA_B11 SMAA_B4 SMAA_B5 SCKE_A3 SCKE_A0 SMAA_A11 SMAA_A12 SCKE_A2 SCKE_A1 SCKE_B0 SCKE_B3 SCKE_B2 SMAA_B12 SCKE_B1 SCS_B1# SCS_B0# SCS_B2# SWE_B# SCAS_B# Ball Number AF21 AJ22 AL21 AK27 AG25 AP20 AL20 AN23 AN21 AM20 AN19 AK19 AE18 AG19 AJ20 AF19 T29 U26 V25 W27 W31
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Table 67. XOR Excluded Pins
Signal Name BLUE BLUE# BPRI# BREQ0# CPURST# DEFER# DREFCLK GCLKIN DVOB_CROMP GREEN GREEN# GVREF TESTP141 HCLKN HCLKP HDRCOMP HDSWING HDVREF HTRDY# HI_COMP HI_VREF HI_SWING PWROK RED RED# REFSET RS0# RS1# RS2# RSTIN# Ball Number H7 G6 B26 B24 E8 L21 G4 H4 AC2 H6 G5 AD2 AC3 C7 B7 E24 C25 F23 D24 AD4 AE2 AE3 AE14 F4 E4 D2 G22 C27 B27 AK4 Signal Name SDM_A0 SDM_A1 SDM_A2 SDM_A3 SDM_A4 SDM_A5 SDM_A6 SDM_A7 SDM_B0 SDM_B1 SDM_B2 SDM_B3 SDM_B4 SDM_B5 SDM_B6 SDM_B7 SMVREF_A0 SMVREF_B0 SMXRCOMP SMXRCOMPVOH SMXRCOMPVOL SMYRCOMP SMYRCOMPVOH SMYRCOMPVOL Reserved TESTIN# CI_RCOMP CI_VREF CI_VSWING Ball Number AP12 AP16 AM24 AP30 AF31 W33 M34 H32 AG11 AG15 AE21 AJ28 AC31 U31 M29 J31 E34 AP9 AK9 AN9 AL9 AA33 R34 R33 AG9 AG10 AG2 AF4 AF2
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Intel(R) 82865G/82865GV GMCH Datasheet

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